diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-12-12 10:27:11 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-10 06:31:52 +0200 |
| commit | ce727e18f0992126b7a27b8a51b426834e804390 (patch) | |
| tree | 7253a5a3c3f343e5e725b72c027127db1354454e /src/soc/intel/baytrail/romstage | |
| parent | be2512973d04f3da3cebfd3e7ee10809fbe4ae4a (diff) | |
baytrail: allow ramstage_cache_location() usage in ramstage
To prepare for caching reference code for S3 resume the
ramstage cache needs to be accesible in ramstage as well.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. S3 resumed.
Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179776
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5012
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/romstage')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 8436c65d17..cb884bd0f1 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -355,19 +355,6 @@ static void *setup_stack_and_mttrs(void) return slot; } -struct ramstage_cache *ramstage_cache_location(long *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - return (void *)&smm_base[smm_region_size() - cache_size]; -} - void ramstage_cache_invalid(struct ramstage_cache *cache) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE |