baytrail: Add functions to peek at GPIO input values

- Add functions to peek at GPIO input pad values (need to be used from
  romstage for board ram_id GPIOs)
- Modify UART GPIOs to use existing fn-assignment function

TEST=Manual. Add debug print and verify that GPIO functions return input
values. Also, verify UART still functions in romstage.
BUG=chrome-os-partner:22865

Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4870
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

1 files changed, 3 insertions, 4 deletions

diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c
index dee3be95c3..e46237ac1d 100644
--- a/src/soc/intel/baytrail/romstage/uart.c
+++ b/src/soc/intel/baytrail/romstage/uart.c
@@ -32,8 +32,7 @@ void byt_config_com1_and_enable(void)
 	reg = 1;
 	pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg);
 
-	/* Set up the pads to select the UART function. RXD and TXD are
-	 * 0x520 and 0x530, respectively. */
-	write32(IO_BASE_ADDRESS + 0x520, read32(IO_BASE_ADDRESS + 0x520) | 1);
-	write32(IO_BASE_ADDRESS + 0x530, read32(IO_BASE_ADDRESS + 0x530) | 1);
+	/* Set up the pads to select the UART function */
+	score_select_func(UART_RXD_PAD, 1);
+	score_select_func(UART_TXD_PAD, 1);
 }