diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-18 11:16:20 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-07 22:06:03 +0200 |
| commit | 6f9947a3ec2cf481dbb233660a29f757a8707cf8 (patch) | |
| tree | 9159ad2baa84a44da8291f1ee90b6ddec50611cb /src/soc/intel/baytrail/romstage/romstage.c | |
| parent | bd4ea8cd4d34cdca6aef2914cf880a20bf3025fe (diff) | |
baytrail: enable caching and prefetching in spi controller
The default mode of the SPI controller has prefetching disabled.
That obviously has a performance impact. Enable both caching
and prefetching to make booting faster. This has a significant
impact on streaming data out of SPI.
BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted rambi. Payload loading step went from ~285ms
to ~54ms.
Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177220
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/romstage.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 91637d51ae..8436c65d17 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -41,6 +41,7 @@ #include <baytrail/reset.h> #include <baytrail/romstage.h> #include <baytrail/smm.h> +#include <baytrail/spi.h> static inline uint64_t timestamp_get(void) { @@ -94,6 +95,13 @@ static void program_base_addresses(void) pci_write_config32(lpc_dev, GBASE, reg); } +static void spi_init(void) +{ + const unsigned long bcr = SPI_BASE_ADDRESS + BCR; + /* Enable caching and prefetching in the SPI controller. */ + write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); +} + static inline void mark_ts(struct romstage_params *rp, uint64_t ts) { struct romstage_timestamps *rt = &rp->ts; @@ -124,6 +132,8 @@ void * asmlinkage romstage_main(unsigned long bist, console_init(); + spi_init(); + set_max_freq(); punit_init(); |