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authorAaron Durbin <adurbin@chromium.org>2013-10-07 16:24:44 -0500
committerAaron Durbin <adurbin@google.com>2014-02-11 22:18:59 +0100
commit08a4613219f5a26a2bcf1216deeb08284cb5269a (patch)
tree0bda3f6be049135af087a205cf7c739facdfb718 /src/soc/intel/baytrail/romstage/romstage.c
parent3f5a1ffb83895b325ec54ba0a6d0147f0af5fca8 (diff)
baytrail: adjust cache policy during romstage
The caching policy for romstage was previously using a 32KiB of cache-as-ram for both the MRC wrapper and the romstage stack/data. It also used a 32KiB code cache region. The BWG's limitations for the code and data region before memory is up was wrong. It consists of a 16-way set associative 1MiB cache. As long as enough addresses are not read there isn't a risk of evicting the data/stack. Now create a 64KiB cache-as-ram region split evenly between romstage and the MRC wrapper. Additionally cache the memory just below 4GiB in CBFS size. This will cover any code and read-only data needed. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted quickly with corresponding changes to MRC warpper. CQ-DEPEND=CL:*146175 Change-Id: I021cecb886a9c0622005edc389136d22905d4520 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172150 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4868 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/romstage.c')
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