intel post-car: Consolidate choose_top_of_stack()

Change-Id: I2c49d68ea9a8f52737b6064bc4fa703bdb1af1df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15463
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 1 insertions, 15 deletions

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index a167c90530..d7e8b17648 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -258,20 +258,6 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
 	return stack;
 }
 
-/* Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage. */
-static unsigned long choose_top_of_stack(void)
-{
-	unsigned long stack_top;
-	const unsigned long romstage_ram_stack_size = 0x5000;
-
-	/* cbmem_add() does a find() before add(). */
-	stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
-	                                     romstage_ram_stack_size);
-	stack_top += romstage_ram_stack_size;
-	return stack_top;
-}
-
 /* setup_stack_and_mttrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
 static void *setup_stack_and_mttrs(void)
@@ -283,7 +269,7 @@ static void *setup_stack_and_mttrs(void)
 	uint32_t top_of_ram;
 
 	/* Top of stack needs to be aligned to a 4-byte boundary. */
-	top_of_stack = choose_top_of_stack() & ~3;
+	top_of_stack = romstage_ram_stack_top() & ~3;
 	slot = (void *)top_of_stack;
 	num_mtrrs = 0;