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authorDuncan Laurie <dlaurie@chromium.org>2013-10-28 15:49:34 -0700
committerAaron Durbin <adurbin@google.com>2014-02-24 18:45:57 +0100
commite3f75f8ecaf1aab1bee1f1f79caa35c526c124a5 (patch)
treef88b0b832674601cd00d3c00143e55a70e9719da /src/soc/intel/baytrail/romstage/gfx.c
parente549e94d03305ce142d973ebb1f8383d37d3a491 (diff)
baytrail: Enable GFX device
- Ungate display in PUNIT - Set GSM to 64MB since 32MB is not supported in <C0 stepping - Initialize power management registers in GTT - Execute VBIOS if found BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot to dev screen via HDMI on rambi Change-Id: Idb032c7ea7f16b651b4c921e3429a652fe663a5d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174922 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4907 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/gfx.c')
-rw-r--r--src/soc/intel/baytrail/romstage/gfx.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c
index 3b47ccf954..592d1feaf8 100644
--- a/src/soc/intel/baytrail/romstage/gfx.c
+++ b/src/soc/intel/baytrail/romstage/gfx.c
@@ -37,7 +37,8 @@ void gfx_init(void)
msac = pci_read_config8(gfx_dev, MSAC);
ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK);
- ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_32MB;
+ /* 32MB GSM is not supported with <C0 stepping. */
+ ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB;
/* Enable VGA decoding as well. */
ggc &= ~(GGC_VGA_DISABLE);