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| author | Patrick Georgi <pgeorgi@chromium.org> | 2016-05-02 17:27:01 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-03 19:01:10 +0200 |
| commit | 06a0b567ce207edcc87e5e4484ae6711c5eb1836 (patch) | |
| tree | 33d2dd3b1de4c26a4e77bb24339ccdd370d48150 /src/soc/intel/baytrail/romstage/Makefile.inc | |
| parent | 58a150a1a332a749d38a656be2fe665da2a971c2 (diff) | |
intel/baytrail: use fmap information for code caching
Instead of using CBFS_SIZE from Kconfig, use values generated from fmap.
While at it, make sure that the cached region size is a power of two.
fmap_config is also added to cpu_incs-y, but that doesn't hurt (except
for some miniscule increase in compile time) because it's #if-guarded.
The upside is that dependencies are tracked properly.
Change-Id: I03a919e1381ca3d0e972780b2c7d76c590aaa994
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14573
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/baytrail/romstage/Makefile.inc')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 5086a4e047..aa10ba6a28 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,4 +1,5 @@ cpu_incs-y += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +cpu_incs-y += $(obj)/fmap_config.h romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c |