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authorLee Leahy <leroy.p.leahy@intel.com>2015-06-16 14:33:30 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-06-24 17:03:49 +0200
commit4a8c19cc90464ad215395bd116c9dc95fc682cac (patch)
tree3ce82af088b0bbb782d667a531f54641abeb1dfb /src/soc/intel/baytrail/pcie.c
parentbfdf2489f071d8ee1d1c510e503b488526111eb7 (diff)
FSP 1.1: Bring source up-to-date
Use 3rdparty/blobs subdirectory for binary files Display the MTRRs after TempRamExit and before the MTRR setup Clear all of the variable MTRRs before the MTRR setup Define the FSP attributes location and bits Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the FSP_BOOTLOADER_TOLUM_HOB. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10589 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/pcie.c')
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