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| author | John Zhao <john.zhao@intel.com> | 2020-05-26 17:02:37 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-12 19:29:51 +0000 |
| commit | 21aece86533093ec01a64be42fcb0fe23d5281b8 (patch) | |
| tree | 7e1544eb5e2849da494b66642a04dc512dcb44d7 /src/soc/intel/baytrail/pcie.c | |
| parent | 049ab12c45111bb03bd8f418f7a4223e1497d64f (diff) | |
soc/intel/tigerlake: Add Type-C IOM base address and size macro
This adds Type-C IO Manageability engine base address and size.
Tigerlake EDS(#575681) section 3.4.3 describes host bridge
REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a
port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is
determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000.
IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=:b:156016218
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/pcie.c')
0 files changed, 0 insertions, 0 deletions