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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-14 06:48:28 +0300 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-27 16:14:48 +0000 |
commit | 568a42ab8c975e41ca322e74b92a186c00aff83d (patch) | |
tree | 82fda7a2976b0b32f6ec2a11fccf643fd454cf62 /src/soc/intel/baytrail/memmap.c | |
parent | 44449192abd612b39c894ef019cfed22e151609f (diff) |
intel/baytrail: Use smm_subregion()
Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34739
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/memmap.c')
-rw-r--r-- | src/soc/intel/baytrail/memmap.c | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 94e91ca7a1..015f13c503 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -14,29 +14,26 @@ */ #include <cbmem.h> -#include <stage_cache.h> +#include <cpu/x86/smm.h> #include <soc/iosf.h> -#include <soc/smm.h> -uintptr_t smm_region_start(void) +static uintptr_t smm_region_start(void) { return (iosf_bunit_read(BUNIT_SMRRL) << 20); } +static size_t smm_region_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + void *cbmem_top(void) { return (void *) smm_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; + *start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20; + *size = smm_region_size(); } |