diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 17:17:51 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 12:47:47 +0000 |
| commit | 26b49cc9a3f027ad6af56e5f6fd572805fe0f30f (patch) | |
| tree | 87c9b0cbf3c0863067534eced5598860edd67c95 /src/soc/intel/baytrail/lpe.c | |
| parent | b5320b2dc1a0c2f710929f4a0aa17529b973b62f (diff) | |
soc/intel/baytrail: Align whitespace and comments
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/baytrail/lpe.c')
| -rw-r--r-- | src/soc/intel/baytrail/lpe.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index c41db94813..e31e15e881 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -19,9 +19,10 @@ #include <soc/ramstage.h> #include "chip.h" - -/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB - * address. Just take 1MiB @ 512MiB. */ +/* + * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. + */ #define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_LENGTH (1 << 20) #define FIRMWARE_PCI_REG_BASE 0xa8 @@ -82,10 +83,12 @@ static void setup_codec_clock(struct device *dev) freq_str = "19.2"; reg = CLK_FREQ_19P2MHZ; break; + case 25: freq_str = "25"; reg = CLK_FREQ_25MHZ; break; + default: printk(BIOS_DEBUG, "LPE codec clock not required.\n"); return; @@ -138,7 +141,6 @@ static void lpe_init(struct device *dev) struct soc_intel_baytrail_config *config = config_of(dev); lpe_stash_firmware_info(dev); - setup_codec_clock(dev); if (config->lpe_acpi_mode) |