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authorAaron Durbin <adurbin@chromium.org>2013-10-31 10:46:56 -0500
committerAaron Durbin <adurbin@google.com>2014-02-27 06:35:25 +0100
commitbc69ae9823e9260bee6f2db557a6d26c683f4ad2 (patch)
tree15231d8ddd509c43aa3b676203cbf80549ac1e9b /src/soc/intel/baytrail/iosf.c
parent92fce495a7fa4331b7f1d49d8f8fe6bcb33761d4 (diff)
baytrail: add lpss iosf functions and regs
The low power subsystem devices have a lot of their configuration done in the IOSF sideband message space. Add support for these access methods. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted through depthcharge. Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636 Signed-off-by: Aaron Durbin <adurbin@chromum.org> Reviewed-on: https://chromium-review.googlesource.com/175440 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4921 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/iosf.c')
-rw-r--r--src/soc/intel/baytrail/iosf.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index 7d420cc627..8016446338 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -165,3 +165,25 @@ void iosf_ushphy_write(int reg, uint32_t val)
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
write_iosf_reg(MCR_REG, cr);
}
+
+uint32_t iosf_lpss_read(int reg)
+{
+ uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) |
+ IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) |
+ IOSF_BYTE_EN;
+
+ write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
+ write_iosf_reg(MCR_REG, cr);
+ return read_iosf_reg(MDR_REG);
+}
+
+void iosf_lpss_write(int reg, uint32_t val)
+{
+ uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) |
+ IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) |
+ IOSF_BYTE_EN;
+
+ write_iosf_reg(MDR_REG, val);
+ write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
+ write_iosf_reg(MCR_REG, cr);
+}