diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-11-30 16:42:49 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-12-13 06:09:15 +0000 |
| commit | ae0ea32c52905d6bcb527b04727463bc2d1b9e09 (patch) | |
| tree | 0e016b82dc5dcfde55f108e82bc4de15fc38db4d /src/soc/intel/baytrail/include | |
| parent | 8bb59ca2faee83ba50850900c8b4edf9331ae931 (diff) | |
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2471_02
The headers added are generated as per FSP v2471_02.
Previous FSP version was v2422_01.
Changes Include:
- UPDs description update in FspsUpd.h
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
BUG=b:208336249
BRANCH=None
TEST=Build and boot brya
Change-Id: I4d04652c06a1c1823d3859be209710c273a2ae8c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/include')
0 files changed, 0 insertions, 0 deletions