diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-27 17:09:02 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:19:16 +0000 |
| commit | e32da955b3a4e9674c6c5012e895c79c2696032e (patch) | |
| tree | f6e0099c482ac97a513d7fcf1f669943c64f8034 /src/soc/intel/baytrail/include | |
| parent | bf31983836e7546ce03061280a7c612d86c70fc9 (diff) | |
skylake: ACPI: Clean up and fix XHCI ACPI Device
- Remove the old workarounds for XHCI from broadwell
- Add PMC device to expose bits needed for XHCI workarounds
- Implement the new workarounds for XHCI, the first will set
a bit in the XHCI MMIO and the second will send a message
to the PMC if a bit is set indicating the workaround is available.
- Clean up the HS/SS port defines and remove unnecessary
methods to determine the port count since we only support SPT-LP.
BUG=chrome-os-partner:44622,chrome-os-partner:44518
BRANCH=none
TEST=build and boot on glados, verify that D0 and D3 can be
made to work (by disabling unused USB and the misbehaving camera)
Change-Id: I535c9d22308c45a3b9bf7e4045c3d01481acc19c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a945f8bc2976d57373be2305c5da40a5691f1e88
Original-Change-Id: I7a57051c0a5c4f5408c2d6ff0aecf660100a1aec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295950
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11537
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/include')
0 files changed, 0 insertions, 0 deletions