diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/soc/intel/baytrail/gpio.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/gpio.c')
| -rw-r--r-- | src/soc/intel/baytrail/gpio.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 43e52ef9a0..6a971eac76 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -142,9 +142,9 @@ static void setup_gpios(const struct soc_gpio_map *gpios, reg, pad_conf0, config->pad_conf1, config->pad_val); #endif - write32(reg + PAD_CONF0_REG, pad_conf0); - write32(reg + PAD_CONF1_REG, config->pad_conf1); - write32(reg + PAD_VAL_REG, config->pad_val); + write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0); + write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32((u32 *)(reg + PAD_VAL_REG), config->pad_val); } if (bank->legacy_base != GP_LEGACY_BASE_NONE) @@ -198,7 +198,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], const struct gpio_bank *bank) { - u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET; + u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); u32 val; int i; @@ -206,10 +206,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], for (i=0; i<4; ++i) { val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | dirq[i * 4 + 1] << 8 | dirq[i * 4]; - write32(reg + i * 4, val); + write32(reg + i, val); #ifdef GPIO_DEBUG printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", - reg + i * 4, val); + reg + i, val); #endif } } @@ -233,8 +233,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) */ if (!enable_xdp_tap) { printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); - write32(GPSSUS_PAD_BASE + 0x2fc, 0xc); - write32(GPSSUS_PAD_BASE + 0x2cc, 0xc); + write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc); + write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc); } } |