diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2013-12-06 16:58:10 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-08 07:07:17 +0200 |
| commit | 27351b93c07e62a1b23dd492b625f0eca6e9283a (patch) | |
| tree | 72a0904a7c1ad37fa3d5450460e8ee5f8f05fcf9 /src/soc/intel/baytrail/gpio.c | |
| parent | 70cc9084a51e7f276b20d146fdab5fda6884febb (diff) | |
baytrail: gpio: Make GPIO inputs MMIO by default
The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the
default input GPIO type MMIO.
BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat
/sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic
jack status.
BRANCH=None
Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179169
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4992
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/gpio.c')
| -rw-r--r-- | src/soc/intel/baytrail/gpio.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index a3c2faaa49..aa495914e5 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -60,6 +60,8 @@ static const struct gpio_bank gpncore_bank = { .legacy_base = GP_LEGACY_BASE_NONE, .pad_base = GPNCORE_PAD_BASE, .has_wake_en = 0, + .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, }; static const struct gpio_bank gpscore_bank = { @@ -68,6 +70,8 @@ static const struct gpio_bank gpscore_bank = { .legacy_base = GPSCORE_LEGACY_BASE, .pad_base = GPSCORE_PAD_BASE, .has_wake_en = 0, + .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, }; static const struct gpio_bank gpssus_bank = { @@ -76,6 +80,8 @@ static const struct gpio_bank gpssus_bank = { .legacy_base = GPSSUS_LEGACY_BASE, .pad_base = GPSSUS_PAD_BASE, .has_wake_en = 1, + .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, }; static void setup_gpios(const struct soc_gpio_map *gpios, @@ -83,7 +89,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios, { const struct soc_gpio_map *config; int gpio = 0; - u32 reg; + u32 reg, pad_conf0; u8 set, bit; u32 use_sel[4] = {0}; @@ -120,13 +126,23 @@ static void setup_gpios(const struct soc_gpio_map *gpios, /* Pad configuration registers */ reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; + /* Add correct func to GPIO pad config */ + pad_conf0 = config->pad_conf0; + if (config->is_gpio) + { + if (gpio >= bank->gpio_f1_range_start && + gpio <= bank->gpio_f1_range_end) + pad_conf0 |= PAD_FUNC1; + else + pad_conf0 |= PAD_FUNC0; + } + #ifdef GPIO_DEBUG printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n", - reg, config->pad_conf0, config->pad_conf1, - config->pad_val ); + reg, pad_conf0, config->pad_conf1, config->pad_val); #endif - write32(reg + PAD_CONF0_REG, config->pad_conf0); + write32(reg + PAD_CONF0_REG, pad_conf0); write32(reg + PAD_CONF1_REG, config->pad_conf1); write32(reg + PAD_VAL_REG, config->pad_val); } |