diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-04-24 11:35:28 -0500 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-17 20:50:58 +0100 |
| commit | 59e209af890a7e58f4c74718a2dec567bbd0d58e (patch) | |
| tree | 6be60c5ac320cc60e9871821d529300849202c23 /src/soc/intel/baytrail/chip.h | |
| parent | a081305729938448dc66ed2e9b2c48ef89ea4356 (diff) | |
baytrail: initialize backlight PWM frequency
In order to protect ourselves from the kernel driver not honoring or
placing the correct frequency in the backlight register always set one.
This code path picks 200Hz as the default if nothing is specified in
device tree. It's somewhat arbitrary but that frequency is valid for all
the eDP panel specs we've seen being used on baytrail devices.
BUG=chrome-os-partner:28267
BRANCH=baytrail
TEST=Built and booted in normal mode. Noted register write stuck.
Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196821
Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
Reviewed-on: http://review.coreboot.org/7845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/baytrail/chip.h')
| -rw-r--r-- | src/soc/intel/baytrail/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 0860a9666a..f19055c1bb 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -78,6 +78,7 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipea_power_off_delay; uint16_t gpu_pipea_light_off_delay; uint16_t gpu_pipea_power_cycle_delay; + int gpu_pipea_pwm_freq_hz; int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ uint16_t gpu_pipeb_power_on_delay; @@ -85,6 +86,7 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipeb_power_off_delay; uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; + int gpu_pipeb_pwm_freq_hz; }; extern struct chip_operations soc_intel_baytrail_ops; |