diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-12-09 14:38:57 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-09 05:42:40 +0200 |
| commit | b40e444aee50c4b9768b596f0d7cf726f8d2c10f (patch) | |
| tree | ce52eb52b0234f9755fea0bc39d090547d677975 /src/soc/intel/baytrail/chip.h | |
| parent | 7b35706cf351675fc7b120a1d1d68baa9e2c717c (diff) | |
baytrail: Enable panel and set timings
These need to be set before the kernel will work without
running the VBIOS option rom.
Also necessary is setting the PP_CONTROL register with
the EDP_FORCE_VDD bit.
BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up
Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179364
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5000
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/baytrail/chip.h')
| -rw-r--r-- | src/soc/intel/baytrail/chip.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 43a3efb650..2cc3fd65e3 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -55,6 +55,31 @@ struct soc_intel_baytrail_config { /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; uint32_t sdcard_cap_high; + + /* + * Digital Port Hotplug Enable: + * 0x04 = Enabled, 2ms short pulse + * 0x05 = Enabled, 4.5ms short pulse + * 0x06 = Enabled, 6ms short pulse + * 0x07 = Enabled, 100ms short pulse + */ + int gpu_pipea_hotplug; + int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipea_power_on_delay; + uint16_t gpu_pipea_light_on_delay; + uint16_t gpu_pipea_power_off_delay; + uint16_t gpu_pipea_light_off_delay; + uint16_t gpu_pipea_power_cycle_delay; + uint32_t gpu_pipea_backlight_pwm; + + int gpu_pipeb_hotplug; + int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipeb_power_on_delay; + uint16_t gpu_pipeb_light_on_delay; + uint16_t gpu_pipeb_power_off_delay; + uint16_t gpu_pipeb_light_off_delay; + uint16_t gpu_pipeb_power_cycle_delay; + uint32_t gpu_pipeb_backlight_pwm; }; extern struct chip_operations soc_intel_baytrail_ops; |