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authorAaron Durbin <adurbin@chromium.org>2013-10-29 16:37:10 -0500
committerAaron Durbin <adurbin@google.com>2014-02-27 06:12:43 +0100
commitd7bc23ac8e034de2bf33c50a1f209d7d23250e6b (patch)
tree5e41823bfbb6cdc6b3ef4ef71dfa98164b8b6c61 /src/soc/intel/baytrail/chip.c
parent67633a558a2cc55215565ee8e9079c97acc87171 (diff)
baytrail: add support for disabling south cluster pci devices
When the southcluster pci devices are listed in the devicetree add the ability to perform the proper disabling sequence for turning off devices. This only turns off the pci device interface as well as put the device into D3Hot. It is not yet known how to put the TXE device into D3Hot so it's currently not possible to disable that device. Also, expose the southcluster_enable_dev() function so that other devices can call this if they require doing specific things before disabling the device. The southcluster_enable_dev() is only called on devices found in the devicetree and if they currently have no ops associated with them. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Interrogated output to ensure devices were being properly disabled. Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174644 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4911 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/chip.c')
-rw-r--r--src/soc/intel/baytrail/chip.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index 0f686fa6fa..eedae397b0 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -53,13 +53,17 @@ static struct device_operations cpu_bus_ops = {
static void enable_dev(device_t dev)
{
- printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
- dev_name(dev), dev->path.type);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
+ } else if (dev->path.type == DEVICE_PATH_PCI) {
+ /* Handle south cluster enablement. */
+ if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
+ (dev->ops == NULL || dev->ops->enable == NULL)) {
+ southcluster_enable_dev(dev);
+ }
}
}