diff options
author | Aaron Durbin <adurbin@chromium.org> | 2013-11-04 21:45:52 -0600 |
---|---|---|
committer | Aaron Durbin <adurbin@google.com> | 2014-05-05 23:38:38 +0200 |
commit | 3bde3d74c5574d7855d1845130bdd357bd2cb7e4 (patch) | |
tree | b7f58f0207c6df21c857351673dfd0c1dcaf65af /src/soc/intel/baytrail/acpi/southcluster.asl | |
parent | 014baea1ceda67aa5df8bb4fbf20782893915f81 (diff) |
baytrail: interrupt routing support
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.
There are still a lot of ACPI errors in the kernel with this
change, though.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/soc/intel/baytrail/acpi/southcluster.asl')
-rw-r--r-- | src/soc/intel/baytrail/acpi/southcluster.asl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 87b5b6e386..7aabcf3fa0 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <soc/intel/baytrail/baytrail/iomap.h> + Scope(\) { // IO-Trap at 0x800. This is the ACPI->SMI communication interface. @@ -29,6 +31,21 @@ Scope(\) Offset(0x8), TRP0, 8 // IO-Trap at 0x808 } + + // Intel Legacy Block + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field (ILBS, AnyAcc, NoLock, Preserve) + { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } } Name(_HID,EISAID("PNP0A08")) // PCIe @@ -210,3 +227,9 @@ Method (_OSC, 4) Return (Arg3) } } + +// LPC Bridge 0:1f.0 +#include "lpc.asl" + +// IRQ routing for each PCI device +#include "irqroute.asl" |