baytrail: Add support for LPSS and SCC devices in ACPI mode

This adds the option to put LPSS and SCC devices into ACPI mode
by saving their BAR0 and BAR1 base addresses in a new device
NVS structure that is placed at offset 0x1000 within the global
NVS table.

The Chrome NVS strcture is padded out to 0xf00 bytes so there
is a clean offset to work with as it will need to be used by
depthcharge to know what addresses devices live at.

A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and
the EMMC 4.5 IRQ is changed to 44.

New ACPI code is provided to instantiate the LPSS and SCC devices
with the magic HID values from Intel so the kernel drivers can
locate and use them.

The default is still for devices to be in PCI mode so this does
not have any real effect without it being enabled in the mainboard
devicetree.

Note: this needs the updated IASL compiler which is in the CQ now
because it uses the FixedDMA() ACPI operator.

BUG=chrome-os-partner:23505,chrome-os-partner:24380
CQ-DEPEND=CL:179459,CL:179364
BRANCH=none
TEST=manual tests on rambi device:

1) build and boot with devices still in PCI mode and ensure that
nothing is changed

2) enable lpss_acpi_mode and see I2C devices detected by the kernel
in ACPI mode.  Note that by itself this breaks trackpad probing so
that will need to be implemented before it is enabled.

3) enable scc_acpi_mode and see EMMC and SDCard devices detected by
the kernel in ACPI mode.  Note that this breaks depthcharge use of
the EMMC because it is not longer discoverable as a PCI device.

Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179481
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5004
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 4 insertions, 20 deletions

diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index cd008243ca..b384cea1ec 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -30,7 +30,7 @@ Name(\PICM, 0)		// IOAPIC/8259
  */
 
 
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
+OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
@@ -70,28 +70,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TOLM,	 32,	// 0x34 - Top of Low Memory
 	CBMC,	 32,	// 0x38 - coreboot mem console pointer
 
-	/* Serial IO device BARs */
-	Offset (0x60),
-	S0B0,	32,	// 0x60 - D21:F0 Serial IO SDMA BAR0
-	S1B0,	32,	// 0x64 - D21:F1 Serial IO I2C0 BAR0
-	S2B0,	32,	// 0x68 - D21:F2 Serial IO I2C1 BAR0
-	S3B0,	32,	// 0x6c - D21:F3 Serial IO SPI0 BAR0
-	S4B0,	32,	// 0x70 - D21:F4 Serial IO SPI1 BAR0
-	S5B0,	32,	// 0x74 - D21:F5 Serial IO UAR0 BAR0
-	S6B0,	32,	// 0x78 - D21:F6 Serial IO UAR1 BAR0
-	S7B0,	32,	// 0x7c - D23:F0 Serial IO SDIO BAR0
-	S0B1,	32,	// 0x80 - D21:F0 Serial IO SDMA BAR1
-	S1B1,	32,	// 0x84 - D21:F1 Serial IO I2C0 BAR1
-	S2B1,	32,	// 0x88 - D21:F2 Serial IO I2C1 BAR1
-	S3B1,	32,	// 0x8c - D21:F3 Serial IO SPI0 BAR1
-	S4B1,	32,	// 0x90 - D21:F4 Serial IO SPI1 BAR1
-	S5B1,	32,	// 0x94 - D21:F5 Serial IO UAR0 BAR1
-	S6B1,	32,	// 0x98 - D21:F6 Serial IO UAR1 BAR1
-	S7B1,	32,	// 0x9c - D23:F0 Serial IO SDIO BAR1
-
 	/* ChromeOS specific */
 	Offset (0x100),
 	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+
+	Offset (0x1000),
+	#include <soc/intel/baytrail/acpi/device_nvs.asl>
 }
 
 /* Set flag to enable USB charging in S3 */