diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-12-10 07:41:33 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-09 05:42:52 +0200 |
| commit | ad8d913f42b4dff80502456a08aac06e7fbcd0dd (patch) | |
| tree | 0ed7479199e5211cfa40d938aac5030b742385ed /src/soc/intel/baytrail/acpi/globalnvs.asl | |
| parent | 4cc4b04d8a5c5b2bdc5b0fcd34cf4ae6352b32c2 (diff) | |
baytrail: Basic DPTF framework
This is not complete yet but it compiles and doesn't cause
any issues by itself. It is tied into the EC pretty closely
so that is part of the same commit.
Once we have more of the EC support done it will need some
more work to make use of those new interfaces properly.
BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF
Change-Id: I4b27e38baae18627a275488d77944208950b98bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179459
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5002
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/acpi/globalnvs.asl')
| -rw-r--r-- | src/soc/intel/baytrail/acpi/globalnvs.asl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 2f614a9806..cd008243ca 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -51,6 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PCNT, 8, // 0x11 - Processor count TPMP, 8, // 0x12 - TPM Present and Enabled TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS /* Device Config */ Offset (0x20), @@ -58,6 +59,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S5U1, 8, // 0x21 - Enable USB1 in S5 S3U0, 8, // 0x22 - Enable USB0 in S3 S3U1, 8, // 0x23 - Enable USB1 in S3 + TACT, 8, // 0x24 - Thermal Active trip point + TPSV, 8, // 0x25 - Thermal Passive trip point + TCRT, 8, // 0x26 - Thermal Critical trip point + DPTE, 8, // 0x27 - Enable DPTF /* Base addresses */ Offset (0x30), |