baytrail: Add support for LPSS and SCC devices in ACPI mode

This adds the option to put LPSS and SCC devices into ACPI mode
by saving their BAR0 and BAR1 base addresses in a new device
NVS structure that is placed at offset 0x1000 within the global
NVS table.

The Chrome NVS strcture is padded out to 0xf00 bytes so there
is a clean offset to work with as it will need to be used by
depthcharge to know what addresses devices live at.

A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and
the EMMC 4.5 IRQ is changed to 44.

New ACPI code is provided to instantiate the LPSS and SCC devices
with the magic HID values from Intel so the kernel drivers can
locate and use them.

The default is still for devices to be in PCI mode so this does
not have any real effect without it being enabled in the mainboard
devicetree.

Note: this needs the updated IASL compiler which is in the CQ now
because it uses the FixedDMA() ACPI operator.

BUG=chrome-os-partner:23505,chrome-os-partner:24380
CQ-DEPEND=CL:179459,CL:179364
BRANCH=none
TEST=manual tests on rambi device:

1) build and boot with devices still in PCI mode and ensure that
nothing is changed

2) enable lpss_acpi_mode and see I2C devices detected by the kernel
in ACPI mode.  Note that by itself this breaks trackpad probing so
that will need to be implemented before it is enabled.

3) enable scc_acpi_mode and see EMMC and SDCard devices detected by
the kernel in ACPI mode.  Note that this breaks depthcharge use of
the EMMC because it is not longer discoverable as a PCI device.

Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179481
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5004
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 87 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl
new file mode 100644
index 0000000000..fce7b53054
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi/device_nvs.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Device Enabled in ACPI Mode */
+
+S0EN,	8,	// SDMA Enable
+S1EN,	8,	// I2C1 Enable
+S2EN,	8,	// I2C2 Enable
+S3EN,	8,	// I2C3 Enable
+S4EN,	8,	// I2C4 Enable
+S5EN,	8,	// I2C5 Enable
+S6EN,	8,	// I2C6 Enable
+S7EN,	8,	// I2C7 Enable
+S8EN,	8,	// SDMA2 Enable
+S9EN,	8,	// SPI Enable
+SAEN,	8,	// PWM1 Enable
+SBEN,	8,	// PWM2 Enable
+SCEN,	8,	// UART2 Enable
+SDEN,	8,	// UART2 Enable
+C0EN,	8,	// MMC Enable
+C1EN,	8,	// SDIO Enable
+C2EN,	8,	// SD Card Enable
+LPEN,	8,	// LPE Enable
+
+/* BAR 0 */
+
+S0B0,	32,	// SDMA BAR0
+S1B0,	32,	// I2C1 BAR0
+S2B0,	32,	// I2C2 BAR0
+S3B0,	32,	// I2C3 BAR0
+S4B0,	32,	// I2C4 BAR0
+S5B0,	32,	// I2C5 BAR0
+S6B0,	32,	// I2C6 BAR0
+S7B0,	32,	// I2C7 BAR0
+S8B0,	32,	// SDMA2 BAR0
+S9B0,	32,	// SPI BAR0
+SAB0,	32,	// PWM1 BAR0
+SBB0,	32,	// PWM2 BAR0
+SCB0,	32,	// UART1 BAR0
+SDB0,	32,	// UART2 BAR0
+C0B0,	32,	// MMC BAR0
+C1B0,	32,	// SDIO BAR0
+C2B0,	32,	// SD Card BAR0
+LPB0,	32,	// LPE BAR0
+
+/* BAR 1 */
+
+S0B1,	32,	// SDMA BAR1
+S1B1,	32,	// I2C1 BAR1
+S2B1,	32,	// I2C2 BAR1
+S3B1,	32,	// I2C3 BAR1
+S4B1,	32,	// I2C4 BAR1
+S5B1,	32,	// I2C5 BAR1
+S6B1,	32,	// I2C6 BAR1
+S7B1,	32,	// I2C7 BAR1
+S8B1,	32,	// SDMA2 BAR1
+S9B1,	32,	// SPI BAR1
+SAB1,	32,	// PWM1 BAR1
+SBB1,	32,	// PWM2 BAR1
+SCB1,	32,	// UART1 BAR1
+SDB1,	32,	// UART2 BAR1
+C0B1,	32,	// MMC BAR1
+C1B1,	32,	// SDIO BAR1
+C2B1,	32,	// SD Card BAR1
+LPB1,	32,	// LPE BAR1
+
+/* Extra */
+
+LPFW,	32,	// LPE BAR2 Firmware