aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/baytrail/acpi.c
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2014-03-28 10:52:13 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-10-28 17:57:12 +0100
commit31ac9e3a9a53523ad342af55b9a20c3c51cd927a (patch)
tree2166177d25481b6ccf2e47e6617b16f2553f1e6b /src/soc/intel/baytrail/acpi.c
parent89f5292ee63cb6f387c06bfbdb4343cc675bc938 (diff)
baytrail: Configure MSR for 2-core and 4-core P-state configutation
Suggested settings to try for performace regression: 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26211 BRANCH=baytrail TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192573 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/acpi.c')
-rw-r--r--src/soc/intel/baytrail/acpi.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 67e8c0ca89..aae0c9961a 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -354,8 +354,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
vid_min = pattrs->iacore_vids[IACORE_LFM];
/* Set P-states coordination type based on MSR disable bit */
- msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
- coord_type = (msr.lo & SINGLE_PCTL) ? SW_ALL : HW_ALL;
+ coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
/* Max Non-Turbo Frequency */
clock_max = (ratio_max * pattrs->bclk_khz) / 1000;