diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-04-22 10:46:06 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-10-22 03:33:20 +0200 |
| commit | d8c4f2b72462f60ae92a59a976437c2407ec6654 (patch) | |
| tree | 3a89c4830ecb16cde242f012a3d72ec81d169948 /src/soc/intel/baytrail/Makefile.inc | |
| parent | 3511023f341b4416ea61558bd5ecfa2ea8416782 (diff) | |
baytrail: Move MRC cache code to a common directory
This common code can be shared across Intel SOCs.
Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196263
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/baytrail/Makefile.inc')
| -rw-r--r-- | src/soc/intel/baytrail/Makefile.inc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index ce1f2433bb..f5c4c9f6e7 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,7 @@ subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage +subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -13,9 +14,6 @@ romstage-y += memmap.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-y += spi.c smm-y += spi.c ramstage-y += chip.c |