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authorSubrata Banik <subrata.banik@intel.com>2021-06-09 03:54:58 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-06-16 03:47:46 +0000
commit54a3417254858fda03476f6bbbad37d7f8d251e6 (patch)
tree2ca056855e1f76475bc2823d4d994e94bc6903cd /src/soc/intel/apollolake
parent09a6d633aeed5986bb503482ebdf28fc1851c631 (diff)
soc/intel/apollolake: Make use of is_devfn_enabled() function
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on Reef. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/acpi.c3
-rw-r--r--src/soc/intel/apollolake/chip.c7
-rw-r--r--src/soc/intel/apollolake/romstage.c6
3 files changed, 5 insertions, 11 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 34f760ff42..ae202456a0 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -143,7 +143,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
static unsigned long soc_fill_dmar(unsigned long current)
{
- struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -151,7 +150,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
unsigned long tmp;
/* IGD has to be enabled, GFXVTBAR set and enabled. */
- const bool emit_igd = is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten;
+ const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
/* First, add DRHD entries */
if (emit_igd) {
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 7172231c07..9694c67fc6 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -533,7 +533,6 @@ static void glk_fsp_silicon_init_params_cb(
{
#if CONFIG(SOC_INTEL_GEMINILAKE)
uint8_t port;
- struct device *dev;
for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
if (!cfg->usb2eye[port].Usb20OverrideEn)
@@ -549,8 +548,7 @@ static void glk_fsp_silicon_init_params_cb(
cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
}
- dev = pcidev_path_on_root(SA_GLK_DEVFN_GMM);
- silconfig->Gmm = is_dev_enabled(dev);
+ silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM);
/* On Geminilake, we need to override the default FSP PCIe de-emphasis
* settings using the device tree settings. This is because PCIe
@@ -693,8 +691,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
/* Set VTD feature according to devicetree */
silconfig->VtdEnable = cfg->enable_vtd;
- dev = pcidev_path_on_root(SA_DEVFN_IGD);
- silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
+ silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
silconfig->PavpEnable = CONFIG(PAVP);
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 0aa6c397e3..13a55dc3b5 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -256,12 +256,10 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
static void parse_devicetree_setting(FSPM_UPD *m_upd)
{
- DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
-
#if CONFIG(SOC_INTEL_GEMINILAKE)
- m_upd->FspmConfig.TraceHubEn = is_dev_enabled(dev);
+ m_upd->FspmConfig.TraceHubEn = is_devfn_enabled(PCH_DEVFN_NPK);
#else
- m_upd->FspmConfig.NpkEn = is_dev_enabled(dev);
+ m_upd->FspmConfig.NpkEn = is_devfn_enabled(PCH_DEVFN_NPK);
#endif
}