diff options
| author | Nelson, Cole <colex.nelson@intel.com> | 2016-11-11 14:17:37 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-17 15:18:47 +0100 |
| commit | 1cf5b87f48668055e531a13c143abf697934dc80 (patch) | |
| tree | ea503567ebe17dc2de4aa95e20fcf2f63ed11227 /src/soc/intel/apollolake | |
| parent | e34e178ca3f31064e9c4cced4243524d08579007 (diff) | |
soc/intel/apollolake: Enable and Lock AES feature register
Configure MPinit feature register during boot and s3 resume.
Enable and Lock Advanced Encryption Standard (AES-NI) feature.
BUG=chrome-os-partner:56922
BRANCH=None
Change-Id: Id16f62ec4e7463a466c43d67f2b03e07e324fa93
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/17396
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 3 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e2d3a9dae7..916d7c5cf4 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -43,6 +43,12 @@ static const struct reg_script core_msr_script[] = { REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), /* Disable support for MONITOR and MWAIT instructions */ REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), + /* + * Enable and Lock the Advanced Encryption Standard (AES-NI) + * feature register + */ + REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, + FEATURE_CONFIG_LOCK), REG_SCRIPT_END }; diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 66fc29babc..38ce4ff913 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -66,6 +66,9 @@ void set_max_freq(void); #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) #define MSR_POWER_CTL 0x1fc #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) |