diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-07 17:13:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-28 08:35:29 +0000 |
| commit | 7837c203d615fce03c6d89d99ba9a746619e49d4 (patch) | |
| tree | ba3626a10a35bd99108228611b18e7f76b7abd02 /src/soc/intel/apollolake | |
| parent | 210b351df3cc070f103feb01a40be9811af87906 (diff) | |
soc/intel/common/block: Move p2sb common functions into block/p2sb
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/p2sb.h | 25 |
2 files changed, 28 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ead6bf3f03..f9c62282ff 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/systemagent.h> @@ -54,12 +55,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) bootblock_systemagent_early_init(); - dev = PCH_DEV_P2SB; - /* BAR and MMIO enable for PCR-Space, so that GPIOs can be configured */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + p2sb_enable_bar(); + p2sb_configure_hpet(); /* Decode the ACPI I/O port range for early firmware verification.*/ dev = PCH_DEV_PMC; diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h new file mode 100644 index 0000000000..01ba7ffd24 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/p2sb.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_P2SB_H_ +#define _SOC_P2SB_H_ + +/* PCI config space registers */ +#define HPTC_OFFSET 0x60 +#define HPTC_ADDR_ENABLE_BIT (1 << 7) + +#define PCH_P2SB_EPMASK0 0xB0 + +#endif /* _SOC_P2SB_H_ */ |