diff options
| author | Marx Wang <marx.wang@intel.com> | 2020-04-07 16:58:38 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 09:57:03 +0000 |
| commit | abc17d10d6feac38cd6c5cdecab04cedfb2bccae (patch) | |
| tree | af55c7ddae9a4d0579a2622b49aba4d84240ac90 /src/soc/intel/apollolake | |
| parent | efc3d04af2f0cbf3d0afeceeadb1d1e09039047d (diff) | |
soc/intel/apollolake: Disable XHCI LFPS power management
Provide the option to disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.
BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 31 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 8 |
2 files changed, 39 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1075642517..c4e068d41f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -99,6 +99,10 @@ /* IOSF Gasket Backbone Local Clock Gating Enable */ #define IOSFGBLCGE (1 << 0) +#define CFG_XHCPMCTRL 0x80a4 +/* BIT[7:4] LFPS periodic sampling for USB3 Ports */ +#define LFPS_PM_DISABLE_MASK 0xFFFFFF0F + const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -829,6 +833,30 @@ static int check_xdci_enable(void) return !!dev->enabled; } +static void disable_xhci_lfps_pm(void) +{ + struct soc_intel_apollolake_config *cfg; + + cfg = config_of_soc(); + + if (cfg->disable_xhci_lfps_pm) { + void *addr; + const struct resource *res; + uint32_t reg; + struct device *xhci_dev = PCH_DEV_XHCI; + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL); + reg = read32(addr); + printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg); + if (reg) { + reg &= LFPS_PM_DISABLE_MASK; + write32(addr, reg); + printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n"); + } + } +} + void platform_fsp_notify_status(enum fsp_notify_phase phase) { if (phase == END_OF_FIRMWARE) { @@ -876,6 +904,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) IOSFGBLCGE; write32(cfg, reg); } + + /* Disable XHCI LFPS power management if the option in dev tree is set. */ + disable_xhci_lfps_pm(); } } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c7974a6cd5..ac36b702ab 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -184,6 +184,14 @@ struct soc_intel_apollolake_config { * the Upd parameter VtdEnable. */ uint8_t enable_vtd; + + /* Options to disable the LFPS periodic sampling for USB3 Ports. + * Default value of PMCTRL_REG bits[7:4] is 9 which means periodic sampling + * interval is 9ms. + * Set 1 to update XHCI host MMIO BAR + PMCTRL_REG (0x80A4 bits[7:4]) to 0 + * 0:Enable (default), 1:Disable. + */ + uint8_t disable_xhci_lfps_pm; }; typedef struct soc_intel_apollolake_config config_t; |