soc/intel: Consolidate FSP CAR setup and teardown code

This patch adds following changes,

- APL, CFL, DENVERTON soc's using same implementation to setup and
  teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
  cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
  and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
  parameters.

- Coffee lake Soc uses FSPT to support Intel Security features like
  BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
  by programming tempraminit parameters and add FSP_T_XIP default if
  FSP_CAR is selected.

BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
      Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
      without errors.

Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

4 files changed, 36 insertions, 159 deletions

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index ede565ae37..6168f86449 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/x86/cache
 
 bootblock-y += bootblock/bootblock.c
+bootblock-$(CONFIG_FSP_CAR) += fspcar.c
 bootblock-y += car.c
 bootblock-y += heci.c
 bootblock-y += gspi.c
@@ -18,7 +19,6 @@ bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c
-bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
@@ -76,8 +76,6 @@ postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
 postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c
 
-postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
-
 verstage-y += car.c
 verstage-y += i2c.c
 verstage-y += gspi.c
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
deleted file mode 100644
index 4c4fa71b50..0000000000
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_def.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/cr.h>
-#include <cpu/x86/post_code.h>
-
-#include <../../../arch/x86/walkcbfs.S>
-
-#define FSP_HDR_OFFSET 0x94
-
-.global	bootblock_pre_c_entry
-bootblock_pre_c_entry:
-
-.global	cache_as_ram
-cache_as_ram:
-	post_code(0x21)
-
-	/* find fsp in cbfs */
-	lea	fsp_name, %esi
-	mov	$1f, %esp
-	jmp	walkcbfs_asm
-1:
-	cmp	$0, %eax
-	jz	.halt_forever
-	mov	CBFS_FILE_OFFSET(%eax), %ebx
-	bswap	%ebx
-	add	%eax, %ebx
-	add	FSP_HDR_OFFSET, %ebx
-
-	/*
-	 * ebx = FSP INFO HEADER
-	 * Calculate entry into FSP
-	 */
-	mov	0x30(%ebx), %eax	/* Load TempRamInitEntryOffset */
-	add	0x1c(%ebx), %eax	/* add the FSP ImageBase */
-
-	/*
-	 * Pass early init variables on a fake stack (no memory yet)
-	 * as well as the return location
-	 */
-	lea	CAR_init_stack, %esp
-
-	/* call FSP binary to setup temporary stack */
-	jmp	*%eax
-
-/*
- * If the TempRamInit API is successful, then when returning, the ECX and
- * EDX registers will point to the temporary but writeable memory range
- * available to the bootloader where ECX is the start and EDX is the end of
- * the range i.e. [ECX,EDX).  See Apollo Lake FSP Integration Guide for more
- * information.
- *
- * Return Values:
- * EAX | Return Status
- * ECX | Temporary Memory Start
- * EDX | Temporary Memory End
- * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call
- */
-
-CAR_init_done:
-
-	/* Setup bootblock stack */
-	mov	%edx, %esp
-
-	/* clear CAR_GLOBAL area as it is not shared */
-	cld
-	xor	%eax, %eax
-	movl	$(_car_global_end), %ecx
-	movl	$(_car_global_start), %edi
-	sub	%edi, %ecx
-	rep	stosl
-
-	/* We can call into C functions now */
-	call	bootblock_c_entry
-
-	/* Never reached */
-
-.halt_forever:
-	post_code(POST_DEAD_CODE)
-	hlt
-	jmp	.halt_forever
-
-CAR_init_params:
-	.long	0                                 /* Microcode Location */
-	.long	0                                 /* Microcode Length */
-	.long	0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
-	.long	CONFIG_ROM_SIZE                  /* Total Firmware Length */
-
-CAR_init_stack:
-	.long	CAR_init_done
-	.long	CAR_init_params
-
-fsp_name:
-	.ascii	"blobs/fspt.bin\x00"
diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S
deleted file mode 100644
index fbf2d31dc3..0000000000
--- a/src/soc/intel/apollolake/exit_car_fsp.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cr.h>
-
-/*
- * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
- * This version of chipset_teardown_car sets up the stack, then bypasses
- * the rest of arch/x86/exit_car.S and calls main() itself instead of
- * returning to _start. In main(), the TempRamExit FSP API is called
- * to tear down the CAR and set up caching which can be overwritten
- * after the API call.  More info can be found in the Apollo Lake FSP
- * Integration Guide included with the FSP binary.  The below
- * caching settings are based on an 8MiB Flash Size given as a
- * parameter to TempRamInit.
- *
- *	TempRamExit MTRR Settings:
- *	0x00000000  - 0x0009FFFF           | Write Back
- *	0x000C0000  - Top of Low Memory    | Write Back
- *	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
- *	0x100000000 - Top of High Memory   | Write Back
- */
-
-.text
-.global chipset_teardown_car
-chipset_teardown_car:
-
-	/* Set up new stack. */
-	mov	post_car_stack_top, %esp
-
-	/* Call C code */
-	call	main
diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c
new file mode 100644
index 0000000000..8b1089f397
--- /dev/null
+++ b/src/soc/intel/apollolake/fspcar.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <bootblock_common.h>
+#include <FsptUpd.h>
+
+const FSPT_UPD temp_ram_init_params = {
+	.FspUpdHeader = {
+		.Signature = 0x545F4450554C5041ULL,	/* 'APLUPD_T' */
+		.Revision = 1,
+		.Reserved = {0},
+	},
+	.FsptCommonUpd = {
+		.Revision = 0,
+		.Reserved = {0},
+		.MicrocodeRegionBase = 0,
+		.MicrocodeRegionLength = 0,
+		.CodeRegionBase =
+			(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
+		.CodeRegionLength = (uint32_t)CONFIG_ROM_SIZE,
+		.Reserved1 = {0},
+	},
+};