soc/intel/common/block: Move common uart function to block/uart

This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.

BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.

Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

7 files changed, 75 insertions, 122 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 4577e76a72..3e84a50cc6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -170,12 +170,7 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133
 
-config CONSOLE_UART_BASE_ADDRESS
-	depends on CONSOLE_SERIAL
-	hex
-	default 0xde000000
-
-config SOC_UART_DEBUG
+config UART_DEBUG
 	bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
 	default n
 	select CONSOLE_SERIAL
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 8a37ae41e6..08a5037683 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -17,7 +17,7 @@ bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
-bootblock-$(CONFIG_SOC_UART_DEBUG) += uart.c
+bootblock-$(CONFIG_UART_DEBUG) += uart.c
 bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
@@ -25,7 +25,7 @@ romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gspi.c
 romstage-y += heci.c
 romstage-y += i2c.c
-romstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
+romstage-$(CONFIG_UART_DEBUG) += uart.c
 romstage-y += memmap.c
 romstage-y += meminit.c
 ifeq ($(CONFIG_SOC_INTEL_GLK),y)
@@ -42,7 +42,7 @@ smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += spi.c
-smm-$(CONFIG_SOC_UART_DEBUG) += uart.c
+smm-$(CONFIG_UART_DEBUG) += uart.c
 smm-y += elog.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -57,7 +57,7 @@ ramstage-y += i2c.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
-ramstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
+ramstage-$(CONFIG_UART_DEBUG) += uart.c
 ramstage-y += nhlt.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
@@ -72,7 +72,7 @@ postcar-y += memmap.c
 postcar-y += mmap_boot.c
 postcar-y += spi.c
 postcar-y += i2c.c
-postcar-$(CONFIG_SOC_UART_DEBUG) += uart.c
+postcar-$(CONFIG_UART_DEBUG) += uart.c
 
 postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S
 
@@ -82,7 +82,7 @@ verstage-y += gspi.c
 verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
-verstage-$(CONFIG_SOC_UART_DEBUG) += uart.c
+verstage-$(CONFIG_UART_DEBUG) += uart.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-y += spi.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index f9c62282ff..bc5c1709fc 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -25,13 +25,13 @@
 #include <intelblocks/rtc.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/uart.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
-#include <soc/uart.h>
 #include <spi-generic.h>
 #include <timestamp.h>
 
@@ -95,8 +95,8 @@ void bootblock_soc_early_init(void)
 	pmc_global_reset_enable(0);
 
 	/* Prepare UART for serial console. */
-	if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
-		pch_uart_init();
+	if (IS_ENABLED(CONFIG_UART_DEBUG))
+		uart_bootblock_init();
 
 	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
 		tpm_enable();
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 479882f47c..eea1e6199b 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -54,4 +54,12 @@
 #define EARLY_I2C_BASE_ADDRESS		0xfe020000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
 
+#define UART_BASE_SIZE			0x1000
+
+#define UART_BASE_0_ADDRESS		0xddffc000
+/* UART BARs are 4KB in size */
+#define UART_BASE_0_ADDR(x)	(UART_BASE_0_ADDRESS + (2 * \
+					UART_BASE_SIZE * (x)))
+#define UART_BASE(x)		UART_BASE_0_ADDR(x)
+
 #endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
deleted file mode 100644
index bf8b9d74e3..0000000000
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_APOLLOLAKE_UART_H_
-#define _SOC_APOLLOLAKE_UART_H_
-
-/* Initialize the console UART including the pads for the configured UART. */
-void pch_uart_init(void);
-
-#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index d2353f1743..416877103c 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -47,7 +47,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
-#include <soc/uart.h>
 #include <spi_flash.h>
 #include <string.h>
 #include <timestamp.h>
@@ -252,7 +251,7 @@ asmlinkage void car_stage_entry(void)
 static void fill_console_params(FSPM_UPD *mupd)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
-		if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) {
+		if (IS_ENABLED(CONFIG_UART_DEBUG)) {
 			mupd->FspmConfig.SerialDebugPortDevice =
 					CONFIG_UART_FOR_CONSOLE;
 			/* use MMIO port type */
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
index a59b567e56..875bc49575 100644
--- a/src/soc/intel/apollolake/uart.c
+++ b/src/soc/intel/apollolake/uart.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015-2017 Intel Corp.
+ * Copyright (C) 2015-2018 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,96 +20,71 @@
  * shouldn't cause any fragmentation.
  */
 
-#include <cbmem.h>
-#include <console/uart.h>
-#include <device/device.h>
-#include <device/pci.h>
+#include <assert.h>
 #include <intelblocks/uart.h>
 #include <soc/gpio.h>
-#include <soc/nvs.h>
 #include <soc/pci_devs.h>
-#include <soc/uart.h>
+#include <string.h>
 
-static const struct pad_config uart_gpios[] = {
+/* UART pad configuration. Support RXD and TXD for now. */
+const struct uart_gpio_pad_config uart_gpio_pads[] = {
 #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPSS_UART0_RXD */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPSS_UART0_TXD */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPSS_UART2_RXD */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, HIZCRx1,
-		DISPUPD), /* LPSS_UART2_TXD */
+	{
+		.console_index = 0,
+		.gpios = {
+			PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1,
+				HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
+			PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1,
+				HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
+
+		},
+	},
+	{
+		.console_index = 2,
+		.gpios = {
+			PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1,
+				HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
+			PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1,
+				HIZCRx1, DISPUPD), /* LPSS_UART2_TXD */
+		},
+	},
 #else
-	PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),		/* UART1 RX */
-	PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),		/* UART1 TX */
-	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),		/* UART2 RX */
-	PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1),		/* UART2 TX */
+	{
+		.console_index = 1,
+		.gpios = {
+			PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
+			PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
+		},
+	},
+	{
+		.console_index = 2,
+		.gpios = {
+			PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
+			PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
+		},
+	},
 #endif
 };
 
-static inline int invalid_uart_for_console(void)
-{
-	/* There are actually only 2 UARTS, and they are named UART1 and
-	 * UART2. They live at pci functions 1 and 2 respectively. */
-	if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1)
-		return 1;
-	return 0;
-}
+const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
 
-void pch_uart_init(void)
+struct device *soc_uart_console_to_device(int uart_console)
 {
-	uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
-#if defined(__SIMPLE_DEVICE__)
-	pci_devfn_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
-#else
-	struct device *uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
-#endif
-
-	/* Get a 0-based pad index. See invalid_uart_for_console() above. */
-	const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
-
-	if (invalid_uart_for_console())
-		return;
-
-	/* Configure the 2 pads per UART. */
-	gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
-
-	/* Program UART2 BAR0, command, reset and clock register */
-	uart_common_init(uart, base);
-
-}
-
-#if !ENV_SMM
-void pch_uart_read_resources(struct device *dev)
-{
-	pci_dev_read_resources(dev);
-
-	if (IS_ENABLED(CONFIG_SOC_UART_DEBUG) &&
-		uart_is_debug_controller(dev)) {
-		/* will override existing resource. */
-		fixed_mem_resource(dev, PCI_BASE_ADDRESS_0,
-				CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0);
+	/*
+	 * if index is valid, this function will return corresponding structure
+	 * for uart console else will return NULL.
+	 */
+	switch (uart_console) {
+	case 0:
+		return (struct device *)PCH_DEV_UART0;
+	case 1:
+		return (struct device *)PCH_DEV_UART1;
+	case 2:
+		return (struct device *)PCH_DEV_UART2;
+	case 3:
+		return (struct device *)PCH_DEV_UART3;
+	default:
+		printk(BIOS_ERR, "Invalid UART console index\n");
+		return NULL;
 	}
 }
-#endif
-
-bool pch_uart_init_debug_controller_on_resume(void)
-{
-	global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
-	if (gnvs)
-		return !!gnvs->uior;
-
-	return false;
-}
-
-device_t pch_uart_get_debug_controller(void)
-{
-	return _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE);
-}
-
-uintptr_t uart_platform_base(int idx)
-{
-	return CONFIG_CONSOLE_UART_BASE_ADDRESS;
-}