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authorAndrey Petrov <andrey.petrov@intel.com>2016-07-14 09:52:00 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-15 18:21:54 +0200
commit89e7b49a114f60f2fddf5f409dea0025785d4604 (patch)
treeafefa7d92b76026ee6da60119cd23430b78272e4 /src/soc/intel/apollolake
parentd779605c29a1630a256c8a1c4966214c580481ec (diff)
soc/intel/apollolake: Consolidate ISH enabling
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/chip.h3
2 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9d08c57015..accc1bb1d0 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -396,8 +396,6 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
if (cfg->emmc_rx_cmd_data_cntl2 != 0)
silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
- silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
-
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable setting of EISS bit in FSP. */
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index bcc81070a9..a1df4810ca 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -93,9 +93,6 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
- /* Integrated Sensor Hub */
- uint8_t integrated_sensor_hub_enable;
-
/* I2C bus configuration */
struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX];