soc/intel/apollolake: Bring in delta for GLK SOC

Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

16 files changed, 751 insertions, 96 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index fdbd6d7622..a9774dc191 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -3,6 +3,13 @@ config SOC_INTEL_APOLLOLAKE
 	help
 	  Intel Apollolake support
 
+config SOC_INTEL_GLK
+	bool
+	default n
+	select SOC_INTEL_APOLLOLAKE
+	help
+	  Intel GLK support
+
 if SOC_INTEL_APOLLOLAKE
 
 config CPU_SPECIFIC_OPTIONS
@@ -275,7 +282,8 @@ config NHLT_DA7219
 
 choice
 	prompt "Cache-as-ram implementation"
-	default CAR_CQOS
+	default CAR_CQOS if !SOC_INTEL_GLK
+	default CAR_NEM
 	help
 	  This option allows you to select how cache-as-ram (CAR) is set up.
 
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index bf445e5628..af4efc191b 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,9 +9,7 @@ subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/x86/cache
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
-bootblock-y += gpio_apl.c
 bootblock-y += heci.c
 bootblock-y += i2c.c
 bootblock-y += lpc_lib.c
@@ -23,7 +21,6 @@ bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
-romstage-y += gpio_apl.c
 romstage-y += heci.c
 romstage-y += i2c.c
 romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
@@ -37,7 +34,6 @@ romstage-y += spi.c
 
 smm-y += mmap_boot.c
 smm-y += pmutil.c
-smm-y += gpio_apl.c
 smm-y += smihandler.c
 smm-y += spi.c
 smm-y += uart_early.c
@@ -48,7 +44,6 @@ ramstage-y += chip.c
 ramstage-y += cse.c
 ramstage-y += elog.c
 ramstage-y += dsp.c
-ramstage-y += gpio_apl.c
 ramstage-y += graphics.c
 ramstage-y += heci.c
 ramstage-y += i2c.c
@@ -87,8 +82,24 @@ verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-y += spi.c
 
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+bootblock-y += gpio_glk.c
+romstage-y += gpio_glk.c
+smm-y += gpio_glk.c
+ramstage-y += gpio_glk.c
+else
+bootblock-y += gpio_apl.c
+romstage-y += gpio_apl.c
+smm-y += gpio_apl.c
+ramstage-y += gpio_apl.c
+endif
+
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
+ifeq ($(CONFIG_SOC_INTEL_GLK),y)
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk
+else
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/apollolake
+endif
 
 # Since FSP-M runs in CAR we need to relocate it to a specific address
 $(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR)
diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl
index 3e99f0966f..960993a835 100644
--- a/src/soc/intel/apollolake/acpi/gpiolib.asl
+++ b/src/soc/intel/apollolake/acpi/gpiolib.asl
@@ -73,7 +73,8 @@ Scope (\_SB)
 		Store (0, Local1)
 		Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS),
 					Local1, Local1)
-		Or( Add (PAD_CFG_BASE, Multiply (Arg1, 8)), Local1, Local1)
+		Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply (
+			GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1)
 		Return (Local1)
 	}
 
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 729134b933..dc81161598 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -33,7 +33,11 @@
 #include <timestamp.h>
 
 static const struct pad_config tpm_spi_configs[] = {
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
+#else
 	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
+#endif
 };
 
 static void tpm_enable(void)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cd7fa62b1f..f72173da8c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015 - 2017 Intel Corp.
  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
  * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
  *
@@ -445,11 +445,56 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig)
 	}
 }
 
+static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
+	*cfg, FSP_S_CONFIG *silconfig)
+{
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these
+					 fields in FspsUpd.h yet */
+	uint8_t port;
+
+	for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
+		if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
+			silconfig->PortUsb20PerPortTxPeHalf[port] =
+				cfg->usb2eye[port].Usb20PerPortTxPeHalf;
+
+		if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
+			silconfig->PortUsb20PerPortPeTxiSet[port] =
+				cfg->usb2eye[port].Usb20PerPortPeTxiSet;
+
+		if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
+			silconfig->PortUsb20PerPortTxiSet[port] =
+				cfg->usb2eye[port].Usb20PerPortTxiSet;
+
+		if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
+			silconfig->PortUsb20HsSkewSel[port] =
+				cfg->usb2eye[port].Usb20HsSkewSel;
+
+		if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
+			silconfig->PortUsb20IUsbTxEmphasisEn[port] =
+				cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
+
+		if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
+			silconfig->PortUsb20PerPortRXISet[port] =
+				cfg->usb2eye[port].Usb20PerPortRXISet;
+
+		if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
+			silconfig->PortUsb20HsNpreDrvSel[port] =
+				cfg->usb2eye[port].Usb20HsNpreDrvSel;
+	}
+#endif
+}
+
+static void glk_fsp_silicon_init_params_cb(
+	struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
+{
+	silconfig->Gmm = 0;
+	silconfig->HdaEnable = 0;
+}
+
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 {
 	FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
 	static struct soc_intel_apollolake_config *cfg;
-	uint8_t port;
 
 	/* Load VBT before devicetree-specific config. */
 	silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
@@ -506,38 +551,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
 	/* Bios config lockdown Audio clk and power gate */
 	silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
-
-	/* USB2 eye diagram settings per port */
-	for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
-		if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
-			silconfig->PortUsb20PerPortTxPeHalf[port] =
-				cfg->usb2eye[port].Usb20PerPortTxPeHalf;
-
-		if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
-			silconfig->PortUsb20PerPortPeTxiSet[port] =
-				cfg->usb2eye[port].Usb20PerPortPeTxiSet;
-
-		if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
-			silconfig->PortUsb20PerPortTxiSet[port] =
-				cfg->usb2eye[port].Usb20PerPortTxiSet;
-
-		if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
-			silconfig->PortUsb20HsSkewSel[port] =
-				cfg->usb2eye[port].Usb20HsSkewSel;
-
-		if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
-			silconfig->PortUsb20IUsbTxEmphasisEn[port] =
-				cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
-
-		if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
-			silconfig->PortUsb20PerPortRXISet[port] =
-				cfg->usb2eye[port].Usb20PerPortRXISet;
-
-		if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
-			silconfig->PortUsb20HsNpreDrvSel[port] =
-				cfg->usb2eye[port].Usb20HsNpreDrvSel;
-	}
-
+	if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+		glk_fsp_silicon_init_params_cb(cfg, silconfig);
+	else
+		apl_fsp_silicon_init_params_cb(cfg, silconfig);
 }
 
 struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index caf749f25f..22e3c80305 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -76,6 +76,8 @@ static struct device_operations cpu_dev_ops = {
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 },
 	{ X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 },
+	{ X86_VENDOR_INTEL, CPUID_GLK_A0 },
+	{ X86_VENDOR_INTEL, CPUID_GLK_B0 },
 	{ 0, 0 },
 };
 
diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c
new file mode 100644
index 0000000000..fd73270d22
--- /dev/null
+++ b/src/soc/intel/apollolake/gpio_glk.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct pad_community glk_gpio_communities[] = {
+	{
+		.port = PID_GPIO_NW,
+		.first_pad = NW_OFFSET,
+		.last_pad = GPIO_214,
+		.num_gpi_regs = NUM_NW_GPI_REGS,
+		.gpi_status_offset = 0,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_NORTHWEST",
+		.acpi_path = "\\_SB.GPO0",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, {
+		.port = PID_GPIO_N,
+		.first_pad = N_OFFSET,
+		.last_pad = GPIO_155,
+		.num_gpi_regs = NUM_N_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_NORTH",
+		.acpi_path = "\\_SB.GPO1",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, {
+		.port = PID_GPIO_AUDIO,
+		.first_pad = AUDIO_OFFSET,
+		.last_pad = GPIO_175,
+		.num_gpi_regs = NUM_AUDIO_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_AUDIO",
+		.acpi_path = "\\_SB.GPO2",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, {
+		.port = PID_GPIO_SCC,
+		.first_pad = SCC_OFFSET,
+		.last_pad = GPIO_209,
+		.num_gpi_regs = NUM_SCC_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS +
+			NUM_AUDIO_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_SCC",
+		.acpi_path = "\\_SB.GPO3",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	},
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(glk_gpio_communities);
+	return glk_gpio_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+	static const struct pmc_to_gpio_route routes[] = {
+		{ PMC_GPE_NW_31_0, GPIO_GPE_NW_31_0 },
+		{ PMC_GPE_NW_63_32, GPIO_GPE_NW_63_32 },
+		{ PMC_GPE_N_31_0, GPIO_GPE_N_31_0 },
+		{ PMC_GPE_N_63_32, GPIO_GPE_N_63_32 },
+		{ PMC_GPE_N_95_64, GPIO_GPE_N_95_64 },
+	};
+	*num = ARRAY_SIZE(routes);
+	return routes;
+}
diff --git a/src/soc/intel/apollolake/include/FspUpd.h b/src/soc/intel/apollolake/include/FspUpd.h
deleted file mode 100644
index d98c42e10b..0000000000
--- a/src/soc/intel/apollolake/include/FspUpd.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
-  list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
-  list of conditions and the following disclaimer in the documentation and/or
-  other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
-  be used to endorse or promote products derived from this software without
-  specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-  THE POSSIBILITY OF SUCH DAMAGE.
-
-  This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(push, 1)
-
-#define FSPT_UPD_SIGNATURE            0x545F4450554C5041        /* 'APLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE            0x4D5F4450554C5041        /* 'APLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE            0x535F4450554C5041        /* 'APLUPD_S' */
-
-#pragma pack(pop)
-
-#endif
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 386ac52d2c..10e0595900 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -20,6 +20,8 @@
 
 #define CPUID_APOLLOLAKE_A0	0x506c8
 #define CPUID_APOLLOLAKE_B0	0x506c9
+#define CPUID_GLK_A0		0x706a0
+#define CPUID_GLK_B0		0x706a1
 
 /* Common Timer Copy (CTC) frequency - 19.2MHz. */
 #define CTC_FREQ		19200000
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index a4d766beba..20d2993ce2 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -17,7 +17,11 @@
 #ifndef _SOC_APL_GPIO_H_
 #define _SOC_APL_GPIO_H_
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#include <soc/gpio_glk.h>
+#else
 #include <soc/gpio_apl.h>
-#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in
-				soc/gpio_apl.h */
+#endif
+#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in
+				soc/gpio_glk.h and soc/gpio_apl.h */
 #endif
diff --git a/src/soc/intel/apollolake/include/soc/gpio_glk.h b/src/soc/intel/apollolake/include/soc/gpio_glk.h
new file mode 100644
index 0000000000..0253981064
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/gpio_glk.h
@@ -0,0 +1,492 @@
+/*
+ *
+ * Placed in a separate file since some of these definitions can be used from
+ * assembly code
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_GLK_GPIO_H_
+#define _SOC_GLK_GPIO_H_
+
+/* North West community pads */
+/* For DFx GPIO, Display, USB, I2C, UART, and Thermal GPIO*/
+#define NW_OFFSET			0
+#define GPIO_0				(NW_OFFSET + 0)
+#define GPIO_1				(NW_OFFSET + 1)
+#define GPIO_2				(NW_OFFSET + 2)
+#define GPIO_3				(NW_OFFSET + 3)
+#define GPIO_4				(NW_OFFSET + 4)
+#define GPIO_5				(NW_OFFSET + 5)
+#define GPIO_6				(NW_OFFSET + 6)
+#define GPIO_7				(NW_OFFSET + 7)
+#define GPIO_8				(NW_OFFSET + 8)
+#define GPIO_9				(NW_OFFSET + 9)
+#define GPIO_10				(NW_OFFSET + 10)
+#define GPIO_11				(NW_OFFSET + 11)
+#define GPIO_12				(NW_OFFSET + 12)
+#define GPIO_13				(NW_OFFSET + 13)
+#define GPIO_14				(NW_OFFSET + 14)
+#define GPIO_15				(NW_OFFSET + 15)
+#define GPIO_16				(NW_OFFSET + 16)
+#define GPIO_17				(NW_OFFSET + 17)
+#define GPIO_18				(NW_OFFSET + 18)
+#define GPIO_19				(NW_OFFSET + 19)
+#define GPIO_20				(NW_OFFSET + 20)
+#define GPIO_21				(NW_OFFSET + 21)
+#define GPIO_22				(NW_OFFSET + 22)
+#define GPIO_23				(NW_OFFSET + 23)
+#define GPIO_24				(NW_OFFSET + 24)
+#define GPIO_25				(NW_OFFSET + 25)
+#define GPIO_26				(NW_OFFSET + 26)
+#define GPIO_27				(NW_OFFSET + 27)
+#define GPIO_28				(NW_OFFSET + 28)
+#define GPIO_29				(NW_OFFSET + 29)
+#define GPIO_30				(NW_OFFSET + 30)
+#define GPIO_31				(NW_OFFSET + 31)
+#define GPIO_32				(NW_OFFSET + 32)
+#define GPIO_33				(NW_OFFSET + 33)
+#define GPIO_34				(NW_OFFSET + 34)
+#define GPIO_35				(NW_OFFSET + 35)
+#define GPIO_36				(NW_OFFSET + 36)
+#define GPIO_37				(NW_OFFSET + 37)
+#define GPIO_38				(NW_OFFSET + 38)
+#define GPIO_39				(NW_OFFSET + 39)
+#define GPIO_40				(NW_OFFSET + 40)
+#define GPIO_41				(NW_OFFSET + 41)
+#define GPIO_42				(NW_OFFSET + 42)
+#define GPIO_43				(NW_OFFSET + 43)
+#define GPIO_44				(NW_OFFSET + 44)
+#define GPIO_45				(NW_OFFSET + 45)
+#define GPIO_46				(NW_OFFSET + 46)
+#define GPIO_47				(NW_OFFSET + 47)
+#define GPIO_48				(NW_OFFSET + 48)
+#define GPIO_49				(NW_OFFSET + 49)
+#define GPIO_50				(NW_OFFSET + 50)
+#define GPIO_51				(NW_OFFSET + 51)
+#define GPIO_52				(NW_OFFSET + 52)
+#define GPIO_53				(NW_OFFSET + 53)
+#define GPIO_54				(NW_OFFSET + 54)
+#define GPIO_55				(NW_OFFSET + 55)
+#define GPIO_56				(NW_OFFSET + 56)
+#define GPIO_57				(NW_OFFSET + 57)
+#define GPIO_58				(NW_OFFSET + 58)
+#define GPIO_59				(NW_OFFSET + 59)
+#define GPIO_60				(NW_OFFSET + 60)
+#define GPIO_61				(NW_OFFSET + 61)
+#define GPIO_62				(NW_OFFSET + 62)
+#define GPIO_63				(NW_OFFSET + 63)
+#define GPIO_64				(NW_OFFSET + 64)
+#define GPIO_65				(NW_OFFSET + 65)
+#define GPIO_66				(NW_OFFSET + 66)
+#define GPIO_67				(NW_OFFSET + 67)
+#define GPIO_68				(NW_OFFSET + 68)
+#define GPIO_69				(NW_OFFSET + 69)
+#define GPIO_70				(NW_OFFSET + 70)
+#define GPIO_71				(NW_OFFSET + 71)
+#define GPIO_72				(NW_OFFSET + 72)
+#define GPIO_73				(NW_OFFSET + 73)
+#define GPIO_74				(NW_OFFSET + 74)
+#define GPIO_75				(NW_OFFSET + 75)
+#define GPIO_211			(NW_OFFSET + 76)
+#define GPIO_212			(NW_OFFSET + 77)
+#define GPIO_213			(NW_OFFSET + 78)
+#define GPIO_214			(NW_OFFSET + 79)
+#define TOTAL_NW_PADS			80
+
+/* North Community Pads */
+/* For power management GPIO, I2C, Display, LPC/eSPI, SPI */
+#define N_OFFSET			(NW_OFFSET + 80)
+#define GPIO_76				(N_OFFSET + 0)
+#define GPIO_77				(N_OFFSET + 1)
+#define GPIO_78				(N_OFFSET + 2)
+#define GPIO_79				(N_OFFSET + 3)
+#define GPIO_80				(N_OFFSET + 4)
+#define GPIO_81				(N_OFFSET + 5)
+#define GPIO_82				(N_OFFSET + 6)
+#define GPIO_83				(N_OFFSET + 7)
+#define GPIO_84				(N_OFFSET + 8)
+#define GPIO_85				(N_OFFSET + 9)
+#define GPIO_86				(N_OFFSET + 10)
+#define GPIO_87				(N_OFFSET + 11)
+#define GPIO_88				(N_OFFSET + 12)
+#define GPIO_89				(N_OFFSET + 13)
+#define GPIO_90				(N_OFFSET + 14)
+#define GPIO_91				(N_OFFSET + 15)
+#define GPIO_92				(N_OFFSET + 16)
+#define GPIO_93				(N_OFFSET + 17)
+#define GPIO_94				(N_OFFSET + 18)
+#define GPIO_95				(N_OFFSET + 19)
+#define GPIO_96				(N_OFFSET + 20)
+#define GPIO_97				(N_OFFSET + 21)
+#define GPIO_98				(N_OFFSET + 22)
+#define GPIO_99				(N_OFFSET + 23)
+#define GPIO_100			(N_OFFSET + 24)
+#define GPIO_101			(N_OFFSET + 25)
+#define GPIO_102			(N_OFFSET + 26)
+#define GPIO_103			(N_OFFSET + 27)
+#define GPIO_104			(N_OFFSET + 28)
+#define GPIO_105			(N_OFFSET + 29)
+#define GPIO_106			(N_OFFSET + 30)
+#define GPIO_107			(N_OFFSET + 31)
+#define GPIO_108			(N_OFFSET + 32)
+#define GPIO_109			(N_OFFSET + 33)
+#define GPIO_110			(N_OFFSET + 34)
+#define GPIO_111			(N_OFFSET + 35)
+#define GPIO_112			(N_OFFSET + 36)
+#define GPIO_113			(N_OFFSET + 37)
+#define GPIO_114			(N_OFFSET + 38)
+#define GPIO_115			(N_OFFSET + 39)
+#define GPIO_116			(N_OFFSET + 40)
+#define GPIO_117			(N_OFFSET + 41)
+#define GPIO_118			(N_OFFSET + 42)
+#define GPIO_119			(N_OFFSET + 43)
+#define GPIO_120			(N_OFFSET + 44)
+#define GPIO_121			(N_OFFSET + 45)
+#define GPIO_122			(N_OFFSET + 46)
+#define GPIO_123			(N_OFFSET + 47)
+#define GPIO_124			(N_OFFSET + 48)
+#define GPIO_125			(N_OFFSET + 49)
+#define GPIO_126			(N_OFFSET + 50)
+#define GPIO_127			(N_OFFSET + 51)
+#define GPIO_128			(N_OFFSET + 52)
+#define GPIO_129			(N_OFFSET + 53)
+#define GPIO_130			(N_OFFSET + 54)
+#define GPIO_131			(N_OFFSET + 55)
+#define GPIO_132			(N_OFFSET + 56)
+#define GPIO_133			(N_OFFSET + 57)
+#define GPIO_134			(N_OFFSET + 58)
+#define GPIO_135			(N_OFFSET + 59)
+#define GPIO_136			(N_OFFSET + 60)
+#define GPIO_137			(N_OFFSET + 61)
+#define GPIO_138			(N_OFFSET + 62)
+#define GPIO_139			(N_OFFSET + 63)
+#define GPIO_140			(N_OFFSET + 64)
+#define GPIO_141			(N_OFFSET + 65)
+#define GPIO_142			(N_OFFSET + 66)
+#define GPIO_143			(N_OFFSET + 67)
+#define GPIO_144			(N_OFFSET + 68)
+#define GPIO_145			(N_OFFSET + 69)
+#define GPIO_146			(N_OFFSET + 70)
+#define GPIO_147			(N_OFFSET + 71)
+#define GPIO_148			(N_OFFSET + 72)
+#define GPIO_149			(N_OFFSET + 73)
+#define GPIO_150			(N_OFFSET + 74)
+#define GPIO_151			(N_OFFSET + 75)
+#define GPIO_152			(N_OFFSET + 76)
+#define GPIO_153			(N_OFFSET + 77)
+#define GPIO_154			(N_OFFSET + 78)
+#define GPIO_155			(N_OFFSET + 79)
+#define TOTAL_N_PADS			80
+
+/* Audio Community Pads */
+#define AUDIO_OFFSET			(N_OFFSET + 80)
+#define GPIO_156			(AUDIO_OFFSET + 0)
+#define GPIO_157			(AUDIO_OFFSET + 1)
+#define GPIO_158			(AUDIO_OFFSET + 2)
+#define GPIO_159			(AUDIO_OFFSET + 3)
+#define GPIO_160			(AUDIO_OFFSET + 4)
+#define GPIO_161			(AUDIO_OFFSET + 5)
+#define GPIO_162			(AUDIO_OFFSET + 6)
+#define GPIO_163			(AUDIO_OFFSET + 7)
+#define GPIO_164			(AUDIO_OFFSET + 8)
+#define GPIO_165			(AUDIO_OFFSET + 9)
+#define GPIO_166			(AUDIO_OFFSET + 10)
+#define GPIO_167			(AUDIO_OFFSET + 11)
+#define GPIO_168			(AUDIO_OFFSET + 12)
+#define GPIO_169			(AUDIO_OFFSET + 13)
+#define GPIO_170			(AUDIO_OFFSET + 14)
+#define GPIO_171			(AUDIO_OFFSET + 15)
+#define GPIO_172			(AUDIO_OFFSET + 16)
+#define GPIO_173			(AUDIO_OFFSET + 17)
+#define GPIO_174			(AUDIO_OFFSET + 18)
+#define GPIO_175			(AUDIO_OFFSET + 19)
+#define TOTAL_AUDIO_PADS		20
+
+
+/* SCC community pads */
+/* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */
+#define SCC_OFFSET			(AUDIO_OFFSET + 20)
+#define GPIO_176			(SCC_OFFSET + 0)
+#define GPIO_177			(SCC_OFFSET + 1)
+#define GPIO_178			(SCC_OFFSET + 2)
+#define GPIO_187			(SCC_OFFSET + 3)
+#define GPIO_179			(SCC_OFFSET + 4)
+#define GPIO_180			(SCC_OFFSET + 5)
+#define GPIO_181			(SCC_OFFSET + 6)
+#define GPIO_182			(SCC_OFFSET + 7)
+#define GPIO_183			(SCC_OFFSET + 8)
+#define GPIO_184			(SCC_OFFSET + 9)
+#define GPIO_185			(SCC_OFFSET + 10)
+#define GPIO_186			(SCC_OFFSET + 11)
+#define GPIO_188			(SCC_OFFSET + 12)
+#define GPIO_210			(SCC_OFFSET + 13)
+#define GPIO_189			(SCC_OFFSET + 14)
+#define GPIO_190			(SCC_OFFSET + 15)
+#define GPIO_191			(SCC_OFFSET + 16)
+#define GPIO_192			(SCC_OFFSET + 17)
+#define GPIO_193			(SCC_OFFSET + 18)
+#define GPIO_194			(SCC_OFFSET + 19)
+#define GPIO_195			(SCC_OFFSET + 20)
+#define GPIO_196			(SCC_OFFSET + 21)
+#define GPIO_197			(SCC_OFFSET + 22)
+#define GPIO_198			(SCC_OFFSET + 23)
+#define GPIO_199			(SCC_OFFSET + 24)
+#define GPIO_200			(SCC_OFFSET + 25)
+#define GPIO_201			(SCC_OFFSET + 26)
+#define GPIO_202			(SCC_OFFSET + 27)
+#define GPIO_203			(SCC_OFFSET + 28)
+#define GPIO_204			(SCC_OFFSET + 29)
+#define GPIO_205			(SCC_OFFSET + 30)
+#define GPIO_206			(SCC_OFFSET + 31)
+#define GPIO_207			(SCC_OFFSET + 32)
+#define GPIO_208			(SCC_OFFSET + 33)
+#define GPIO_209			(SCC_OFFSET + 34)
+#define TOTAL_SCC_PADS			35
+#define TOTAL_PADS			(SCC_OFFSET + 35)
+
+/*
+ * Miscellaneous Configuration register(MISCCFG).These are community specific
+ * registers and are meant to house miscellaneous configuration fields per
+ * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
+ */
+#define GPIO_MISCCFG		0x10 /* Miscellaneous Configuration offset */
+
+#define GPIO_GPE_NW_31_0	0
+#define GPIO_GPE_NW_63_32	1
+#define GPIO_GPE_NW_95_63	2
+#define GPIO_GPE_N_31_0		3
+#define GPIO_GPE_N_63_32	4
+#define GPIO_GPE_N_95_64	5
+#define GPIO_GPE_AUDIO_31_0	6
+#define GPIO_GPE_SCC_31_0	7
+#define GPIO_GPE_SCC_63_32	8
+
+#define GPIO_MAX_NUM_PER_GROUP	32
+
+#define MISCCFG_GPE0_DW0_SHIFT 8
+#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
+#define MISCCFG_GPE0_DW1_SHIFT 12
+#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
+#define MISCCFG_GPE0_DW2_SHIFT 16
+#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+
+/* Host Software Pad Ownership Register.
+ * The pins in the community are divided into 3 groups :
+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
+ */
+#define HOSTSW_OWN_REG_0		0xB0
+
+#define GPI_INT_EN_0			0x110
+
+#define GPI_SMI_STS_0			0x170
+#define GPI_SMI_EN_0			0x190
+
+/* PERST_0 not defined */
+#define GPIO_PRT0_UDEF			0xFF
+
+#define NUM_NW_PADS			(TOTAL_NW_PADS)
+#define NUM_N_PADS			(TOTAL_N_PADS)
+#define NUM_AUDIO_PADS			(TOTAL_AUDIO_PADS)
+#define NUM_SCC_PADS			(TOTAL_SCC_PADS)
+
+#define NUM_NW_GPI_REGS	\
+	(ALIGN_UP(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_N_GPI_REGS	\
+	(ALIGN_UP(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_AUDIO_GPI_REGS	\
+	(ALIGN_UP(NUM_AUDIO_PADS, GPIO_MAX_NUM_PER_GROUP) /	\
+		GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_SCC_GPI_REGS	\
+	(ALIGN_UP(NUM_SCC_PADS, GPIO_MAX_NUM_PER_GROUP) /	\
+		GPIO_MAX_NUM_PER_GROUP)
+
+
+#define NUM_GPI_STATUS_REGS		(NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
+					+ NUM_AUDIO_GPI_REGS + NUM_SCC_GPI_REGS)
+
+
+/* Macros for translating a global pad offset to a local offset */
+#define PAD_NW(pad)			(pad - NW_OFFSET)
+#define PAD_N(pad)			(pad - N_OFFSET)
+#define PAD_AUDIO(pad)			(pad - AUDIO_OFFSET)
+#define PAD_SCC(pad)			(pad - SCC_OFFSET)
+
+/* Linux names of the GPIO devices. */
+#define GPIO_COMM_NW_NAME		"INT3453:00"
+#define GPIO_COMM_N_NAME		"INT3453:01"
+#define GPIO_COMM_AUDIO_NAME		"INT3453:02"
+#define GPIO_COMM_SCC_NAME		"INT3453:03"
+
+/* Following is used in gpio asl */
+#define GPIO_COMM_NAME			"INT3453"
+#define GPIO_COMM_0_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - Northwest"
+#define GPIO_COMM_1_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - North"
+#define GPIO_COMM_2_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - Audio"
+#define GPIO_COMM_3_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - SCC"
+
+#define GPIO_COMM0_PID			PID_GPIO_NW
+#define GPIO_COMM1_PID			PID_GPIO_N
+#define GPIO_COMM2_PID			PID_GPIO_AUDIO
+#define GPIO_COMM3_PID			PID_GPIO_SCC
+
+#define GPIO_8_IRQ	0x32
+#define GPIO_9_IRQ	0x33
+#define GPIO_10_IRQ	0x34
+#define GPIO_11_IRQ	0x35
+#define GPIO_12_IRQ	0x36
+#define GPIO_13_IRQ	0x37
+#define GPIO_14_IRQ	0x38
+#define GPIO_15_IRQ	0x39
+#define GPIO_16_IRQ	0x3a
+#define GPIO_17_IRQ	0x3b
+#define GPIO_18_IRQ	0x3c
+#define GPIO_19_IRQ	0x3d
+#define GPIO_20_IRQ	0x3e
+#define GPIO_21_IRQ	0x3f
+#define GPIO_22_IRQ	0x40
+#define GPIO_23_IRQ	0x41
+#define GPIO_24_IRQ	0x42
+#define GPIO_25_IRQ	0x43
+#define GPIO_26_IRQ	0x44
+#define GPIO_27_IRQ	0x45
+#define GPIO_28_IRQ	0x46
+#define GPIO_29_IRQ	0x47
+#define GPIO_30_IRQ	0x48
+#define GPIO_31_IRQ	0x49
+#define GPIO_32_IRQ	0x4a
+#define GPIO_33_IRQ	0x4b
+#define GPIO_34_IRQ	0x4c
+#define GPIO_35_IRQ	0x4d
+#define GPIO_36_IRQ	0x4e
+#define GPIO_37_IRQ	0x4f
+#define GPIO_38_IRQ	0x50
+#define GPIO_39_IRQ	0x51
+#define GPIO_40_IRQ	0x52
+#define GPIO_41_IRQ	0x53
+#define GPIO_42_IRQ	0x54
+#define GPIO_43_IRQ	0x55
+#define GPIO_44_IRQ	0x56
+#define GPIO_45_IRQ	0x57
+#define GPIO_46_IRQ	0x58
+#define GPIO_47_IRQ	0x59
+#define GPIO_48_IRQ	0x5a
+#define GPIO_49_IRQ	0x5b
+#define GPIO_50_IRQ	0x5c
+#define GPIO_51_IRQ	0x5d
+#define GPIO_52_IRQ	0x5e
+#define GPIO_53_IRQ	0x5f
+#define GPIO_54_IRQ	0x60
+#define GPIO_55_IRQ	0x61
+#define GPIO_56_IRQ	0x62
+#define GPIO_57_IRQ	0x63
+#define GPIO_58_IRQ	0x64
+#define GPIO_59_IRQ	0x65
+#define GPIO_60_IRQ	0x66
+#define GPIO_61_IRQ	0x67
+#define GPIO_62_IRQ	0x68
+#define GPIO_63_IRQ	0x69
+#define GPIO_64_IRQ	0x6a
+#define GPIO_65_IRQ	0x6b
+#define GPIO_66_IRQ	0x6c
+#define GPIO_67_IRQ	0x6d
+#define GPIO_68_IRQ	0x6e
+#define GPIO_69_IRQ	0x6f
+#define GPIO_70_IRQ	0x70
+#define GPIO_71_IRQ	0x71
+#define GPIO_72_IRQ	0x72
+#define GPIO_73_IRQ	0x73
+#define GPIO_211_IRQ	0x74
+#define GPIO_212_IRQ	0x75
+#define GPIO_213_IRQ	0x76
+#define GPIO_214_IRQ	0x77
+#define GPIO_79_IRQ	0x32
+#define GPIO_80_IRQ	0x33
+#define GPIO_81_IRQ	0x34
+#define GPIO_82_IRQ	0x35
+#define GPIO_83_IRQ	0x36
+#define GPIO_84_IRQ	0x37
+#define GPIO_85_IRQ	0x38
+#define GPIO_86_IRQ	0x39
+#define GPIO_87_IRQ	0x3a
+#define GPIO_88_IRQ	0x3b
+#define GPIO_89_IRQ	0x3c
+#define GPIO_90_IRQ	0x3d
+#define GPIO_91_IRQ	0x3e
+#define GPIO_92_IRQ	0x3f
+#define GPIO_93_IRQ	0x40
+#define GPIO_94_IRQ	0x41
+#define GPIO_95_IRQ	0x42
+#define GPIO_96_IRQ	0x43
+#define GPIO_105_IRQ	0x44
+#define GPIO_110_IRQ	0x45
+#define GPIO_111_IRQ	0x46
+#define GPIO_112_IRQ	0x47
+#define GPIO_113_IRQ	0x48
+#define GPIO_114_IRQ	0x49
+#define GPIO_115_IRQ	0x4a
+#define GPIO_116_IRQ	0x4b
+#define GPIO_117_IRQ	0x4c
+#define GPIO_118_IRQ	0x4d
+#define GPIO_119_IRQ	0x4e
+#define GPIO_120_IRQ	0x4f
+#define GPIO_121_IRQ	0x50
+#define GPIO_122_IRQ	0x51
+#define GPIO_123_IRQ	0x52
+#define GPIO_124_IRQ	0x53
+#define GPIO_125_IRQ	0x54
+#define GPIO_126_IRQ	0x55
+#define GPIO_127_IRQ	0x56
+#define GPIO_128_IRQ	0x57
+#define GPIO_129_IRQ	0x58
+#define GPIO_130_IRQ	0x59
+#define GPIO_131_IRQ	0x5a
+#define GPIO_132_IRQ	0x5b
+#define GPIO_133_IRQ	0x5c
+#define GPIO_134_IRQ	0x5d
+#define GPIO_135_IRQ	0x5e
+#define GPIO_136_IRQ	0x5f
+#define GPIO_137_IRQ	0x60
+#define GPIO_138_IRQ	0x61
+#define GPIO_139_IRQ	0x62
+#define GPIO_140_IRQ	0x63
+#define GPIO_141_IRQ	0x64
+#define GPIO_142_IRQ	0x65
+#define GPIO_143_IRQ	0x66
+#define GPIO_144_IRQ	0x67
+#define GPIO_145_IRQ	0x68
+#define GPIO_146_IRQ	0x69
+#define GPIO_147_IRQ	0x6a
+#define GPIO_148_IRQ	0x6b
+#define GPIO_149_IRQ	0x6c
+#define GPIO_150_IRQ	0x6d
+#define GPIO_151_IRQ	0x6e
+#define GPIO_152_IRQ	0x6f
+#define GPIO_153_IRQ	0x70
+#define GPIO_154_IRQ	0x71
+#define GPIO_155_IRQ	0x72
+
+#define PAD_CFG_BASE	0x600
+
+#define GPIO_NUM_PAD_CFG_REGS   4
+
+#endif /* _SOC_GLK_GPIO_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
index b3e976e9fc..ca5cf8427d 100644
--- a/src/soc/intel/apollolake/include/soc/pcr_ids.h
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -19,11 +19,16 @@
 /*
  * Port ids.
  */
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define PID_GPIO_AUDIO	0xC9
+#define PID_GPIO_SCC	0xC8
+#else
 #define PID_GPIO_SW	0xC0
 #define PID_GPIO_S	0xC2
+#define PID_GPIO_W	0xC7
+#endif
 #define PID_GPIO_NW	0xC4
 #define PID_GPIO_N	0xC5
-#define PID_GPIO_W	0xC7
 #define PID_ITSS	0xD0
 #define PID_RTC		0xD1
 
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index b6b6e7b5e2..4744b89814 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -180,6 +180,17 @@
 #define  GPE0_DW2_SHIFT		8
 #define  GPE0_DW3_SHIFT		12
 
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+#define PMC_GPE_N_95_64		8
+#define PMC_GPE_N_63_32		7
+#define PMC_GPE_N_31_0		6
+#define PMC_GPE_NW_127_96	5
+#define PMC_GPE_NW_95_64	4
+#define PMC_GPE_NW_63_32	3
+#define PMC_GPE_NW_31_0		2
+#define PMC_GPE_SCC_63_32	1
+#define PMC_GPE_SCC_31_0	0
+#else  /*For APL*/
 #define  PMC_GPE_SW_31_0	0
 #define  PMC_GPE_SW_63_32	1
 #define  PMC_GPE_NW_31_0	3
@@ -188,6 +199,7 @@
 #define  PMC_GPE_N_31_0		6
 #define  PMC_GPE_N_63_32	7
 #define  PMC_GPE_W_31_0		9
+#endif
 
 /* Track power state from reset to log events. */
 struct chipset_power_state {
diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c
index 08c16a7362..08a97b1f19 100644
--- a/src/soc/intel/apollolake/lpc_lib.c
+++ b/src/soc/intel/apollolake/lpc_lib.c
@@ -46,6 +46,25 @@ static const struct lpc_mmio_range {
 };
 
 static const struct pad_config lpc_gpios[] = {
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_CLKOUT0 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_CLKOUT1 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_AD0 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_AD1 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_AD2 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_AD3 */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_154, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_CLKRUNB */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPC_FRAMEB*/
+#else
 	PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
@@ -55,6 +74,7 @@ static const struct pad_config lpc_gpios[] = {
 	PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
 	PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
 	PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
+#endif
 };
 
 void lpc_configure_pads(void)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 7c9268af14..9dad15fc3a 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -165,10 +165,12 @@ static bool punit_init(void)
 			PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
 			PUINT_THERMAL_DEVICE_IRQ_LOCK;
 
-	data = MCHBAR32(0x7818);
-	data &= 0xFFFFE01F;
-	data |= 0x20 | 0x200;
-	MCHBAR32(0x7818) = data;
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) {
+		data = MCHBAR32(0x7818);
+		data &= 0xFFFFE01F;
+		data |= 0x20 | 0x200;
+		MCHBAR32(0x7818) = data;
+	}
 
 	/* Stage0 BIOS Reset Complete (RST_CPL) */
 	enable_bios_reset_cpl();
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 311e580636..4c143ad854 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -37,10 +37,21 @@ uintptr_t uart_platform_base(int idx)
 }
 
 static const struct pad_config uart_gpios[] = {
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPSS_UART0_RXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPSS_UART0_TXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPSS_UART2_RXD */
+	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, HIZCRx1,
+		DISPUPD), /* LPSS_UART2_TXD */
+#else
 	PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),		/* UART1 RX */
 	PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),		/* UART1 TX */
 	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),		/* UART2 RX */
 	PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1),		/* UART2 TX */
+#endif
 };
 
 void pch_uart_init(void)