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authorKeith Short <keithshort@chromium.org>2019-05-09 11:40:34 -0600
committerDuncan Laurie <dlaurie@chromium.org>2019-05-22 17:44:53 +0000
commit15588b03b36aa875e2a2a31cc649a2d9dff7581e (patch)
tree70c054b070ca0b4f962b362d06ff62ef8a7454e9 /src/soc/intel/apollolake
parent24302633a558e545efcc84178136bd1879f6d8ee (diff)
post_code: add post code for hardware initialization failure
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/memmap.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 4f91b8aea5..6058e34895 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -40,7 +40,8 @@ void *cbmem_top(void)
config = dev->chip_info;
if (!config)
- die("Failed to get chip_info\n");
+ die_with_post_code(POST_HW_INIT_FAILURE,
+ "Failed to get chip_info\n");
/* FSP allocates 2x PRMRR Size Memory for alignment */
if (config->sgx_enable)