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authorElyes HAOUAS <ehaouas@noos.fr>2016-07-29 18:31:16 +0200
committerMartin Roth <martinroth@google.com>2016-07-31 19:27:53 +0200
commit038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch)
tree8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/intel/apollolake
parentf9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff)
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15963 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/acpi/gpio.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index f2a7e76f20..030d3ebaec 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -146,8 +146,8 @@ scope (\_SB) {
Scope(\_GPE)
{
/* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
- * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in acpi enable
- * register at 0x430. For APL acpi enable register DW0 i.e., ACPI
+ * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable
+ * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI
* GPE0a_EN at 0x430 is reserved.
*/
Method(_L0F, 0) {}