diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-21 03:46:58 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-03-12 08:48:03 +0000 |
| commit | 405f2296892c10a48db50cd66c2eb364cde0806e (patch) | |
| tree | 407fdc4b2df309129ff377912560ffc371a36166 /src/soc/intel/apollolake/uart.c | |
| parent | 2b5892256c734634f1fcbfb1a31bab979f271c22 (diff) | |
soc/intel/*: drop UART pad configuration from common code
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.
Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.
Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/soc/intel/apollolake/uart.c')
| -rw-r--r-- | src/soc/intel/apollolake/uart.c | 57 |
1 files changed, 8 insertions, 49 deletions
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index b8758f56e6..348c2876ad 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -6,59 +6,18 @@ * shouldn't cause any fragmentation. */ -#include <intelblocks/uart.h> -#include <soc/gpio.h> +#include <commonlib/helpers.h> +#include <device/pci_type.h> #include <soc/pci_devs.h> -const struct uart_controller_config uart_ctrlr_config[] = { +const unsigned int uart_devices[] = { + PCH_DEVFN_UART0, #if CONFIG(SOC_INTEL_GEMINILAKE) - { - .console_index = 0, - .devfn = PCH_DEVFN_UART0, - .gpios = { - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1, - HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1, - HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */ - - }, - }, - { - .console_index = 2, - .devfn = PCH_DEVFN_UART2, - .gpios = { - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1, - HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1, - HIZCRx1, DISPUPD), /* LPSS_UART2_TXD */ - }, - }, + PCI_DEVFN_INVALID, #else - { - .console_index = 0, - .devfn = PCH_DEVFN_UART0, - .gpios = { - PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */ - PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */ - }, - }, - { - .console_index = 1, - .devfn = PCH_DEVFN_UART1, - .gpios = { - PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ - PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ - }, - }, - { - .console_index = 2, - .devfn = PCH_DEVFN_UART2, - .gpios = { - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ - }, - }, + PCH_DEVFN_UART1, #endif + PCH_DEVFN_UART2, }; -const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config); +const int uart_devices_size = ARRAY_SIZE(uart_devices); |