diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-06-10 18:01:45 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:50:08 +0200 |
| commit | 7929dd02e68ba52a41c5a8a48b6b7bf8b918677d (patch) | |
| tree | 205f6d9ae144dc4fef2133be8508a4187f799617 /src/soc/intel/apollolake/smihandler.c | |
| parent | 266a1f794dc28053e97794cbeb3f1a588137698b (diff) | |
soc/intel/apollolake: add SMI status bit definitons and use them
Provide the bit definitions for the SMI status register. Also,
utilize them which means deleting some of the handlers that can't
exist because there are no status bits.
BUG=chrome-os-partner:54262
Change-Id: I389c7cb3cad01ba0eca52a337ffee352a2010bfa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15154
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/smihandler.c')
| -rw-r--r-- | src/soc/intel/apollolake/smihandler.c | 36 |
1 files changed, 4 insertions, 32 deletions
diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 580fd71d1f..fd175e30d8 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -44,36 +44,8 @@ const struct smm_save_state_ops *get_smm_save_state_ops(void) } const smi_handler_t southbridge_smi[32] = { - NULL, /* [0] reserved */ - NULL, /* [1] reserved */ - NULL, /* [2] BIOS_STS */ - NULL, /* [3] LEGACY_USB_STS */ - southbridge_smi_sleep, /* [4] SLP_SMI_STS */ - southbridge_smi_apmc, /* [5] APM_STS */ - NULL, /* [6] SWSMI_TMR_STS */ - NULL, /* [7] reserved */ - southbridge_smi_pm1, /* [8] PM1_STS */ - southbridge_smi_gpe0, /* [9] GPE0_STS */ - NULL, /* [10] reserved */ - NULL, /* [11] reserved */ - NULL, /* [12] reserved */ - southbridge_smi_tco, /* [13] TCO_STS */ - southbridge_smi_periodic, /* [14] PERIODIC_STS */ - NULL, /* [15] SERIRQ_SMI_STS */ - NULL, /* [16] SMBUS_SMI_STS */ - NULL, /* [17] LEGACY_USB2_STS */ - NULL, /* [18] INTEL_USB2_STS */ - NULL, /* [19] reserved */ - NULL, /* [20] PCI_EXP_SMI_STS */ - NULL, /* [21] reserved */ - NULL, /* [22] reserved */ - NULL, /* [23] reserved */ - NULL, /* [24] reserved */ - NULL, /* [25] reserved */ - NULL, /* [26] SPI_STS */ - NULL, /* [27] reserved */ - NULL, /* [28] PUNIT */ - NULL, /* [29] GUNIT */ - NULL, /* [30] reserved */ - NULL /* [31] reserved */ + [SLP_SMI_STS] = southbridge_smi_sleep, + [APM_SMI_STS] = southbridge_smi_apmc, + [TCO_SMI_STS] = southbridge_smi_tco, + [PERIODIC_SMI_STS] = southbridge_smi_periodic, }; |