soc/intel/apollolake: utilize postcar phase/stage

The current Apollolake flow has its code executing out of
cache-as-ram for the pre-DRAM stages. This is different from
past platforms where they were just executing-in-place against
the memory-mapped SPI flash boot media. The implication is
that when cache-as-ram needs to be torn down one needs to be
executing out of DRAM since the act of cache-as-ram going
away means the code disappears out from under the processor.
Therefore load and use the postcar infrastructure to bootstrap
this process for tearing down cache-as-ram and subsequently
loading ramstage.

Change-Id: I856f4b992dd2609b95375767bfa4fe64a267d89e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14141
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 7c8924dab4..d24cdf8d3e 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -11,6 +11,7 @@
  * (at your option) any later version.
  */
 
+#include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/symbols.h>
 #include <cbfs.h>
@@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void)
 	void *hob_list_ptr;
 	struct range_entry fsp_mem;
 	struct range_entry reg_car;
+	struct postcar_frame pcf;
 
 	printk(BIOS_DEBUG, "Starting romstage...\n");
 
@@ -109,7 +111,10 @@ asmlinkage void car_stage_entry(void)
 	/* Now that CBMEM is up, save the list so ramstage can use it */
 	fsp_save_hob_list(hob_list_ptr);
 
-	run_ramstage();
+	if (postcar_frame_init(&pcf, 1*KiB))
+		die("Unable to initialize postcar frame.\n");
+
+	run_postcar_phase(&pcf);
 }
 
 static void fill_console_params(struct FSPM_UPD *mupd)