diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2016-05-09 17:18:26 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-06-09 20:25:58 +0200 |
| commit | de4b09fa26f37396ceaaa27d6ca8a038364f1e52 (patch) | |
| tree | ee009b291a3867951b244776480627095febab8d /src/soc/intel/apollolake/romstage.c | |
| parent | 1a718642ead0aa42561e4db30431066d53fdb57c (diff) | |
soc/intel/apollolake: Update FSP header files
Update autogenerated FSP 2.0 generic header files
based on FSP release 136_30.
Changes were made to avoid duplicating some of the
structs for every SoC.
BUG=chrome-os-partner:50765
TEST=Build coreboot
Change-Id: I6f3c9270fb67210d6ea87e17ccf52d203fa64b4b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7145
Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com>
Tested-by: Petrov, Andrey <andrey.petrov@intel.com>
Reviewed-on: https://chromium.devtools.intel.com/7584
Reviewed-on: https://review.coreboot.org/15081
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 434d11fa20..dec5a18601 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -218,7 +218,7 @@ static void fill_console_params(struct FSPM_UPD *mupd) void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) { const struct mrc_saved_data *mrc_cache; - struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + struct FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; struct chipset_power_state *ps = car_get_var_ptr(&power_state); int prev_sleep_state = chipset_prev_sleep_state(ps); @@ -226,12 +226,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) mainboard_memory_init_params(mupd); /* Do NOT let FSP do any GPIO pad configuration */ - mupd->FspmConfig.GpioPadInitTablePtr = NULL; - /* - * At FIT_POINTER there is an address that points to FIT. Even though it - * is technically 64bit value we know only 32bit address is used. - */ - mupd->FspmConfig.FitTablePtr = read32((void*) FIT_POINTER); + mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; /* Reserve enough memory under TOLUD to save CBMEM header */ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); /* @@ -247,18 +242,18 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; #endif - arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; + arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) { /* MRC cache found */ arch_upd->NvsBufferPtr = (void *)mrc_cache->data; - arch_upd->Bootmode = + arch_upd->BootMode = prev_sleep_state == SLEEP_STATE_S3 ? FSP_BOOT_ON_S3_RESUME: FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", - mrc_cache->size, arch_upd->Bootmode); + mrc_cache->size, arch_upd->BootMode); } else printk(BIOS_DEBUG, "MRC cache was not found\n"); } |