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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-17 20:51:08 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-26 21:08:41 +0000 |
| commit | cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch) | |
| tree | b0438431df0943ab5f0fa9d80a99fc265130ac23 /src/soc/intel/apollolake/romstage.c | |
| parent | 16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff) | |
soc/intel: Use common romstage code
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 29 |
1 files changed, 11 insertions, 18 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1464d2c6b3..2c283396c9 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> #include <arch/romstage.h> #include <device/pci_ops.h> #include <arch/symbols.h> @@ -193,20 +192,15 @@ void set_max_freq(void) cpu_set_p_state_to_turbo_ratio(); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; bool s3wake; + size_t var_size; struct chipset_power_state *ps = pmc_get_power_state(); - uintptr_t smm_base; - size_t smm_size, var_size; const void *new_var_data; timestamp_add_now(TS_START_ROMSTAGE); - console_init(); - soc_early_romstage_init(); s3wake = pmc_fill_power_state(ps) == ACPI_S3; @@ -227,10 +221,14 @@ asmlinkage void car_stage_entry(void) else printk(BIOS_ERR, "Failed to determine variable data\n"); - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - mainboard_save_dimm_info(); +} + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; /* * We need to make sure ramstage will be run cached. At this point exact @@ -240,12 +238,9 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* * Cache the TSEG region at the top of ram. This region is * not restricted to SMM mode until SMM has been relocated. @@ -254,9 +249,7 @@ asmlinkage void car_stage_entry(void) * region for other purposes. */ smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); } static void fill_console_params(FSPM_UPD *mupd) |