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| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:09:52 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:31:09 +0200 |
| commit | 932e09d168ba180ee0a17319c1e9cd73009a7adb (patch) | |
| tree | 0109419369f1f8d755ade853f7510580fd36bd7f /src/soc/intel/apollolake/romstage.c | |
| parent | 9fe0ff2f832dc58bfbb51032a7565c75e24a36c1 (diff) | |
drivers/intel/fsp1_1: align on using ACPI_Sx definitions
The SLEEP_STATE_x definitions in the chipsets utilizing
FSP 1.1. driver have the exact same values as the ACPI_Sx
definitions. The chipsets will be moved over subsequently,
but updating this first allows the per-chipset patches
to be isolated.
BUG=chrome-os-partner:54977
Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15665
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
0 files changed, 0 insertions, 0 deletions