diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2016-08-18 13:31:29 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-08-20 08:56:32 +0200 |
| commit | 15f6f3aa588157780ee86ef9dabf608bf093718a (patch) | |
| tree | 71f218ecc6a620f78b54fa8ce37a56be17ff13c8 /src/soc/intel/apollolake/romstage.c | |
| parent | 98e0ee62142a1654195d32a37f57920c2bb348c2 (diff) | |
soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
Read FSP produced memory HOB and use it to populate DIMM info.
DIMM 'part_num' info is stored statically based on memory/SKU id.
BUG=chrome-os-partner:55505
TEST='dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 067d654b25..6b58aa5305 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -118,6 +118,8 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + mainboard_save_dimm_info(); + /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache @@ -170,6 +172,12 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd) printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } +__attribute__ ((weak)) +void mainboard_save_dimm_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + int get_sw_write_protect_state(void) { uint8_t status; |