soc/intel/apollolake: Implement stage cache to improve resume time

This patch enables stage cache to save ~40ms during S3 resume.
It saves ramstage in the stage cache and restores it on resume
so that ramstage does not have to reinitialize during the
resume flow. Stage cache functionality is added to postcar stage
since ramstage is called from postcar.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for Reef and tested ramstage being cached

Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16833
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 15 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index b9733defa3..2384ceb1cf 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -29,6 +29,7 @@
 #include <device/pci_def.h>
 #include <device/resource.h>
 #include <fsp/api.h>
+#include <fsp/memmap.h>
 #include <fsp/util.h>
 #include <soc/iomap.h>
 #include <soc/northbridge.h>
@@ -105,6 +106,9 @@ asmlinkage void car_stage_entry(void)
 	uintptr_t top_of_ram;
 	bool s3wake;
 	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+	void *smm_base;
+	size_t smm_size;
+	uintptr_t tseg_base;
 
 	timestamp_add_now(TS_START_ROMSTAGE);
 
@@ -135,6 +139,17 @@ asmlinkage void car_stage_entry(void)
 		postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
 					MTRR_TYPE_WRPROT);
 
+	/*
+	* Cache the TSEG region at the top of ram. This region is
+	* not restricted to SMM mode until SMM has been relocated.
+	* By setting the region to cacheable it provides faster access
+	* when relocating the SMM handler as well as using the TSEG
+	* region for other purposes.
+	*/
+	smm_region(&smm_base, &smm_size);
+	tseg_base = (uintptr_t)smm_base;
+	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+
 	run_postcar_phase(&pcf);
 }