diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-09 10:59:25 -0800 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-03-13 17:52:40 +0100 |
commit | 07441b5ae6db1d171474b393d98d7da9595bcc8a (patch) | |
tree | e22dfbe505da5cf90320aa07d533beafbd3681db /src/soc/intel/apollolake/romstage.c | |
parent | a4447535968549136668185dac6854e95beb9930 (diff) |
soc/intel/apollolake: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build for reef
Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18728
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
-rw-r--r-- | src/soc/intel/apollolake/romstage.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 9a153b34f4..93b571e586 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -220,7 +220,8 @@ asmlinkage void car_stage_entry(void) top_of_ram = (uintptr_t) cbmem_top(); /* cbmem_top() needs to be at least 16 MiB aligned */ assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) @@ -244,7 +245,8 @@ asmlinkage void car_stage_entry(void) static void fill_console_params(FSPM_UPD *mupd) { if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { - mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + mupd->FspmConfig.SerialDebugPortDevice = + CONFIG_UART_FOR_CONSOLE; /* use MMIO port type */ mupd->FspmConfig.SerialDebugPortType = 2; /* use 4 byte register stride */ |