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authorSubrata Banik <subrata.banik@intel.com>2017-03-05 12:37:00 +0530
committerMartin Roth <martinroth@google.com>2017-03-28 16:39:28 +0200
commit2ee54db24603f51738cbebd6d80c120f2b4db76d (patch)
tree32670a0d223cde958305c1b2288b0f09a9e5a3b0 /src/soc/intel/apollolake/romstage.c
parentfc4c7d8320d329d3712cb74e527dca4178f71bf8 (diff)
soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
This patch to make common PCI device name between APL and SKL. Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
-rw-r--r--src/soc/intel/apollolake/romstage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 93b571e586..38cf81cdc5 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -80,10 +80,10 @@ static uint32_t fsp_version CAR_GLOBAL;
static void soc_early_romstage_init(void)
{
/* Set MCH base address and enable bit */
- pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
+ pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
/* Enable decoding for HPET. Needed for FSP global pointer storage */
- pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
+ pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE);
}
@@ -140,7 +140,7 @@ static bool punit_init(void)
return false;
}
/* Set Punit interrupt pin IPIN offset 3D */
- pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2);
+ pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
/* Set PUINT IRQ to 24 and INTPIN LOCK */
write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ),