diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-05-19 13:44:14 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-06-01 21:48:43 +0200 |
| commit | d18b53f45dca75d82bc011e217edad045add23ef (patch) | |
| tree | 5d3b72c744140c4d7ffea3cc86d95dc87e1fd38c /src/soc/intel/apollolake/romstage.c | |
| parent | f5f7c84a58c61ff690bf9dd4260280e93353d4fe (diff) | |
soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL
Systemagent common code will use MCH_BASE_ADDRESS macro,
hence cleaning current APL code to adhere such changes.
Change-Id: Iace1cf786b08221c3955101186509ac5161c3841
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/romstage.c')
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 39d3989117..87ba26bd34 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -81,7 +81,7 @@ static uint32_t fsp_version CAR_GLOBAL; static void soc_early_romstage_init(void) { /* Set MCH base address and enable bit */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); + pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | @@ -140,11 +140,10 @@ static bool punit_init(void) * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). * Enable all cores here. */ - write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), - 0x0); + write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK), 0x0); + + void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS + BIOS_RESET_CPL); - void *bios_rest_cpl = (void *)(MCH_BASE_ADDR + - P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR); /* P-Unit bring up */ reg = read32(bios_rest_cpl); if (reg == 0xffffffff) { @@ -156,14 +155,14 @@ static bool punit_init(void) pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2); /* Set PUINT IRQ to 24 and INTPIN LOCK */ - write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ), PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_LOCK); - data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data = read32((void *)(MCH_BASE_ADDRESS + 0x7818)); data &= 0xFFFFE01F; data |= 0x20 | 0x200; - write32((void *)(MCH_BASE_ADDR + 0x7818), data); + write32((void *)(MCH_BASE_ADDRESS + 0x7818), data); /* Stage0 BIOS Reset Complete (RST_CPL) */ write32(bios_rest_cpl, 0x1); |