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authorSubrata Banik <subrata.banik@intel.com>2020-09-19 13:20:58 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-21 16:03:16 +0000
commit77cc3267fc970c710299a164ecbc471f9287d719 (patch)
tree9e60471abf75ff30b740d055b97c8159fe78d75f /src/soc/intel/apollolake/reset.c
parente49ce2604fe93d4b2147fd82d86c3a9e629c336c (diff)
soc/intel: Refactor do_global_reset() function
List of changes: 1. Rename do_global_reset() to force_global_reset() 2. Make force_global_reset() function static 3. Implement force_global_reset() into common/reset.c to avoid dedicated SoC implementation 4. Remove redundant force_global_reset() implementation from dedicated SoC 5. Make direct call to global_reset() from cse_lite.c 7. Drop CONFIG_HAVE_CF9_RESET_PREPARE Kconfig from APL SoC due to common reset (soc/intel/common/reset.c) code migration 8. Remove unused function send_global_reset() from SKL me.c due to common reset code migration 9. Delete heci.c from APL SoC as unused Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I1c5dc8d5606ef28ffaed4a64d90f470ae1ffc2a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/reset.c')
-rw-r--r--src/soc/intel/apollolake/reset.c44
1 files changed, 0 insertions, 44 deletions
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 8641b63aaf..7eac9648bc 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -1,52 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <cf9_reset.h>
#include <console/console.h>
-#include <delay.h>
#include <fsp/util.h>
-#include <intelblocks/pmclib.h>
-#include <soc/heci.h>
#include <soc/intel/common/reset.h>
-#include <soc/pm.h>
-#include <timer.h>
-
-#define CSE_WAIT_MAX_MS 1000
-
-void do_global_reset(void)
-{
- pmc_global_reset_enable(1);
- do_full_reset();
-}
-
-void cf9_reset_prepare(void)
-{
- struct stopwatch sw;
-
- /*
- * If CSE state is something else than 'normal', it is probably in some
- * recovery state. In this case there is no point in waiting for it to
- * get ready so we cross fingers and reset.
- */
- if (!heci_cse_normal()) {
- printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n");
- return;
- }
-
- /* Reset if CSE is ready */
- if (heci_cse_done())
- return;
-
- printk(BIOS_SPEW, "CSE is not yet ready, waiting\n");
- stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS);
- while (!heci_cse_done()) {
- if (stopwatch_expired(&sw)) {
- printk(BIOS_SPEW, "CSE timed out. Resetting\n");
- return;
- }
- mdelay(1);
- }
- printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
-}
void chipset_handle_reset(uint32_t status)
{