diff options
author | Furquan Shaikh <furquan@google.com> | 2020-09-21 22:44:27 +0000 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-22 05:13:39 +0000 |
commit | b13bd1efcf568bb220500ca94e4de097f3bed9ec (patch) | |
tree | 498a45a955bbd97da0995a966e9356ae6236ce94 /src/soc/intel/apollolake/reset.c | |
parent | 5bd4adf542abea433c98c72f7423762109412d4d (diff) |
Revert "soc/intel: Refactor do_global_reset() function"
This reverts commit 77cc3267fc970c710299a164ecbc471f9287d719.
Reason for revert: Breaks quark and also needs breaking down into multiple CLs as commented by Nico on CB:45541
Change-Id: Idf4ca74158df15483856754ee24cc4472a8e09b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/reset.c')
-rw-r--r-- | src/soc/intel/apollolake/reset.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c index 7eac9648bc..8641b63aaf 100644 --- a/src/soc/intel/apollolake/reset.c +++ b/src/soc/intel/apollolake/reset.c @@ -1,8 +1,52 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cf9_reset.h> #include <console/console.h> +#include <delay.h> #include <fsp/util.h> +#include <intelblocks/pmclib.h> +#include <soc/heci.h> #include <soc/intel/common/reset.h> +#include <soc/pm.h> +#include <timer.h> + +#define CSE_WAIT_MAX_MS 1000 + +void do_global_reset(void) +{ + pmc_global_reset_enable(1); + do_full_reset(); +} + +void cf9_reset_prepare(void) +{ + struct stopwatch sw; + + /* + * If CSE state is something else than 'normal', it is probably in some + * recovery state. In this case there is no point in waiting for it to + * get ready so we cross fingers and reset. + */ + if (!heci_cse_normal()) { + printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n"); + return; + } + + /* Reset if CSE is ready */ + if (heci_cse_done()) + return; + + printk(BIOS_SPEW, "CSE is not yet ready, waiting\n"); + stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS); + while (!heci_cse_done()) { + if (stopwatch_expired(&sw)) { + printk(BIOS_SPEW, "CSE timed out. Resetting\n"); + return; + } + mdelay(1); + } + printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw)); +} void chipset_handle_reset(uint32_t status) { |