soc/intel/apollolake: Clear RTC failure bit after reading it

This change ensures that the RTC failure bit is cleared in PMCON1
after cmos_init checks for it. Before this change, RPS was cleared
in dev init phase. If any reboot occurred before dev init stage
(e.g. FSP reset) then RPS won't be cleared and cmos_init will
re-initialize CMOS data. This resulted in any information like VBNV
flags stored in CMOS after first cmos_init to be lost.

BUG=b:72879807
BRANCH=coral
TEST=Verified that recovery request is preserved when recovery is
requested without battery on coral.

Change-Id: Ib23b1fcd5c3624bad6ab83dce17a469b2f5b5ba8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 17 insertions, 1 deletions

diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index dbaed70ca3..05590bd8f8 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -232,5 +232,21 @@ int soc_get_rtc_failed(void)
 
 int vbnv_cmos_failed(void)
 {
-	return rtc_failed(read32((void *)(read_pmc_mmio_bar() + GEN_PMCON1)));
+	uintptr_t pmc_bar = read_pmc_mmio_bar();
+	uint32_t gen_pmcon1 = read32((void *)(pmc_bar + GEN_PMCON1));
+	int rtc_failure = rtc_failed(gen_pmcon1);
+
+	if (rtc_failure) {
+		printk(BIOS_INFO, "RTC failed!\n");
+
+		/* We do not want to write 1 to clear-1 bits. Set them to 0. */
+		gen_pmcon1 &= ~GEN_PMCON1_CLR1_BITS;
+
+		/* RPS is write 0 to clear. */
+		gen_pmcon1 &= ~RPS;
+
+		write32((void *)(pmc_bar + GEN_PMCON1), gen_pmcon1);
+	}
+
+	return rtc_failure;
 }