soc/intel/apollolake: Add GPE routing code

This patch adds the basic framework for SCI to GPE routing code.

BUG = chrome-os-partner:53438
TEST = Toogle pch_sci_l from ec console using gpioset command and
	see that the sci counter increases in /sys/firmware/acpi/interrupt
	and also 9 in /proc/interrupts.

Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

1 files changed, 68 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index c88e14c4c0..94040c3650 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -18,8 +18,13 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <console/console.h>
 #include <soc/iomap.h>
 #include <soc/pci_ids.h>
+#include <soc/gpio.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include "chip.h"
 
 /*
  * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases
@@ -58,10 +63,73 @@ static void set_resources(device_t dev)
 	report_resource_stored(dev, res, " ACPI BAR");
 }
 
+static void pmc_gpe_init(void)
+{
+	uint32_t gpio_cfg = 0;
+	uint32_t gpio_cfg_reg;
+	uint8_t dw1, dw2, dw3;
+	const struct soc_intel_apollolake_config *config;
+
+	struct device *dev = NB_DEV_ROOT;
+	if (!dev || !dev->chip_info) {
+		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+		return;
+	}
+	config = dev->chip_info;
+
+	uintptr_t pmc_bar = get_pmc_mmio_bar();
+
+	const uint32_t gpio_cfg_mask =
+		(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
+		(GPE0_DWX_MASK << GPE0_DW2_SHIFT) |
+		(GPE0_DWX_MASK << GPE0_DW3_SHIFT);
+
+	/* Assign to local variable */
+	dw1 = config->gpe0_dw1;
+	dw2 = config->gpe0_dw2;
+	dw3 = config->gpe0_dw3;
+
+	/* Making sure that bad values don't bleed into the other fields */
+	dw1 &= GPE0_DWX_MASK;
+	dw2 &= GPE0_DWX_MASK;
+	dw3 &= GPE0_DWX_MASK;
+
+	/* Route the GPIOs to the GPE0 block. Determine that all values
+	 * are different, and if they aren't use the reset values.
+	 * DW0 is reserved/unused */
+	if (dw1 == dw2 || dw2 == dw3) {
+		printk(BIOS_INFO, "PMC: Using default GPE route.\n");
+		gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG);
+
+		dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK;
+		dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK;
+		dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK;
+	} else {
+		gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT;
+		gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT;
+		gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT;
+	}
+
+	gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask;
+	gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
+
+	write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg);
+
+	/* Set the routes in the GPIO communities as well. */
+	gpio_route_gpe(dw1, dw2, dw3);
+}
+
+static void pmc_init(struct device *dev)
+{
+	/* Set up GPE configuration */
+	pmc_gpe_init();
+}
+
 static const struct device_operations device_ops = {
 	.read_resources		= read_resources,
 	.set_resources		= set_resources,
 	.enable_resources	= pci_dev_enable_resources,
+	.init                   = &pmc_init,
 };
 
 static const struct pci_driver pmc __pci_driver = {